HC230F1020 Altera, HC230F1020 Datasheet - Page 83

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
f
f
f
t
f
f
f
t
f
t
t
t
IN
INPFD
INDUTY
INJITTER
VCO
OUT
OUT_IO
CONFIGPLL
CLBW
LOCK
PLL_PSERR
ARESET
Table 4–43. HardCopy II Fast PLL Specifications (Part 1 of 2)
Name
Input clock frequency for HC210, HC220,
HC230 and HC240 devices
Input clock frequency for the HC210W
device
Input frequency to the PFD
Input clock duty cycle
Input clock jitter tolerance in terms of period
jitter. Bandwidth ≤ 2 MHz
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 0.2 MHz
Upper VCO frequency range for HC210,
HC220, HC230 and HC240 devices
Upper VCO frequency range for HC210W
devices
Lower VCO frequency range for HC210,
HC220, HC230 and HC240 devices
Lower VCO frequency range for HC210W
device
PLL output frequency to GCLK or RCLK
PLL output frequency to LVDS or DPA clock
for HC210, HC220, HC230 and HC240
devices
PLL output frequency to LVDS or DPA clock
for HC210W devices
PLL clock output frequency to regular I/O pin
Time required to reconfigure scan chains for
fast PLLs
PLL closed loop bandwidth
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
Description
4.6875
4.6875
1.16
Min
300
300
150
150
150
150
16
16
16
40
—
—
—
—
—
10
75/f
0.03
SCANCLK
Typ
0.5
—
—
PLL Timing Specifications
—
—
—
—
—
—
—
—
—
—
—
—
1
5
320
1,040
1,040
Max
± 30
717
500
840
520
420
550
840
60
(1)
28
—
—
—
—
1
(1)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
(pp)
(pp)
ms
4–41
ns
ns
ns
ps
ns
%