HC230F1020 Altera, HC230F1020 Datasheet - Page 29

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
provide the same features as the general purpose IOEs except for the PCI
clamping diode. In Stratix II FPGAs, all IOEs support the general purpose
IOE features except the PCI diode, which is only supported on the top
and bottom I/O pins.
The general purpose IOE has many features, including:
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General purpose IOEs support the following I/O standards:
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The general purpose CLK and PLL_FB input pins and the PLL_OUT
output pins support the following I/O standards:
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The programmable drive strengths available vary depending on the I/O
standard being used and are listed in
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
Table 2–10. Programmable Drive Strength Support for General-Purpose
IOEs (Part 1 of 2)
Dedicated single-ended I/O buffers
3.3-V, 64-bit, 66 MHz PCI compliance
3.3-V, 64-bit, 133 MHz PCI-X 1.0 compliance
JTAG boundary-scan test (BST) support
On-chip driver series termination (non-calibrated)
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Open-drain outputs
PCI clamping diode (supported on the bottom I/O pins only)
Double data rate (DDR) registers
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
HyperTransport technology
LVPECL (on input clocks and PLL_OUT only)
I/O Standard
Programmable Drive Strength Options (mA)
Table
2–10.
I/O Structure and Features
4, 8, 12
4, 8, 12
4, 8
Preliminary
2–21