HC230F1020 Altera, HC230F1020 Datasheet - Page 218

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
Figure 8–5. HC240 PLL Locations
Global and Local
Signals
8–30
High-Speed IOEs
High-Speed IOEs
FPLL7CLK
FPLL8CLK
Bank 2
Bank 1
CLK[3..0]
PLL 1
PLL 2
PLL 7
PLL 8
HardCopy II devices have 16 clock pins (CLK[15..0]) to drive either the
global or local clock networks. Four clock pins drive each side of the
device. This is similar to Stratix II devices; therefore, there are no
limitations when compiling designs for Stratix II devices and
HardCopy II companion devices.
Internal logic and enhanced and fast PLL outputs can also drive the
global and regional clock networks. Each global and regional clock
network has a clock control block, which controls the selection of the
clock source and allows you to dynamically enable or disable the clock
network to reduce power consumption.
Memory Interface IOEs
Memory Interface IOEs
Bank 3
Bank 8
Bank 12 Bank 10
Bank 11 Bank 9
PLL 12
PLL 11
CLK[15..12]
CLK[7..4]
PLL 6
PLL 5
Memory Interface IOEs
Memory Interface IOEs
Bank 4
Bank 7
PLL 10
PLL 4
PLL 3
PLL 9
Altera Corporation
FPLL10CLK
CLK[8..11]
FPLL9CLK
September 2008
Bank 5
High-Speed IOEs
Bank 6
High-Speed IOEs