HC230F1020 Altera, HC230F1020 Datasheet - Page 175

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
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For more detailed information about the features and capabilities of the
TimeQuest timing analyzer, refer to the TimeQuest Timing Analyzer
chapter in volume 3 of the Quartus II Handbook.
Using Classic Timing Analyzer
Classic Timing Analyzer analyzes the delay of every design path and
analyzes all timing requirements to ensure correct circuit operation. As
part of the compilation flow, the Quartus II software automatically
performs static timing analysis so that you do not need to launch a
separate timing analysis tool. Classic Timing Analyzer checks every path
in the design against your timing constraints for timing violations and
reports results in the Timing Analysis reports, giving you immediate
access to the data.
Quartus II Timing Related Checks and Settings
The Classic Timing Analyzer provides a number of timing related checks
as you go through a HardCopy II design flow. The HardCopy II Advisor
can guide you through these checks and ensure that you perform all steps
required to successfully complete a HardCopy II design.
For more information on the HardCopy II Advisor and the checks
performed by the Design Assistant, refer to the Design Guidelines for
HardCopy Series Devices chapter in the Hardware Design Considerations
section of the HardCopy Series Handbook.
The HardCopy II Advisor advises on the correct Quartus II settings for
timing analysis
generate accurate and complete timing reports. The list of settings
includes the following:
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In the Classic Timing Analysis flow, you must set the value of
CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS to OFF. Otherwise, the
unconstrained path report (UCP report) will list all clock domain crossing
paths as unconstrained. The report does not honor the ON setting, which
cuts timing from clocks not originating from the same PLL.
Enable Recovery/Removal Analysis
Enable Timing Constraints Check
Report Combined Fast/Slow Timing
Report I/O Paths Separately
Enable Clock Latency
Enable Misc. Timing Assignments
(Figure
7–4). These settings are necessary to ensure you
HardCopy II Timing Closure Methodology
7–11