HC230F1020 Altera, HC230F1020 Datasheet - Page 109

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
Altera strongly recommends that you use the
derive_clock_uncertainty command in the HardCopy II revision.
The HardCopy Design Center will not be accepting designs that do not
have clock uncertainty constraint by either using the
derive_clock_uncertainty command or the HardCopy II Clock
Uncertainty Calculator, and then using the set_clock_uncertainty
command.
For more information on how to use the HardCopy II Clock Uncertainty
Calculator, refer to the HardCopy II Clock Uncertainty User Guide available
on the Altera website at www.altera.com.
Quartus II Software Features Supported for HardCopy II Designs
The Quartus II software supports optimization features for HardCopy II
prototype development, including:
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Physical Synthesis Optimization
To enable Physical Synthesis Optimizations for the Stratix II FPGA
revision of the design, on the Assignments menu, click Settings. In the
Settings dialog box, in the Category list, select Fitter Settings. These
optimizations are migrated into the HardCopy II companion revision for
placement and timing closure. When designing with a HardCopy II
device first, physical synthesis optimizations can be enabled for the
HardCopy II device, and these post-fit optimizations are migrated to the
Stratix II FPGA revision.
LogicLock
The use of LogicLock Regions in the Stratix II FPGA is supported for
designs migrating to HardCopy II. However, LogicLock Regions are not
passed into the HardCopy II Companion Revision. You can use
LogicLock in the HardCopy II design but you must create new
LogicLock Regions in the HardCopy II companion revision. In addition,
LogicLock Regions in HardCopy II devices can not have their properties
set to Auto Size. However, Floating LogicLock regions are supported.
HardCopy II LogicLock Regions must be manually sized and placed in
the floorplan. When LogicLock Regions are created in a HardCopy II
device, they start with width and height dimensions set to (1,1), and the
origin coordinates for placement are at X1_Y1 in the lower left corner of
Physical Synthesis Optimization
LogicLock Regions
PowerPlay Power Analyzer
Incremental Compilation (Synthesis and Fitter)
Maximum Fan-Out Assignments
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Regions
HardCopy II Recommended Settings in the Quartus II Software
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