HC230F1020 Altera, HC230F1020 Datasheet - Page 30

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
2–22
Preliminary
General purpose IOEs support non-calibrated on-chip series termination.
50- and 25-Ω on-chip series termination is available for 3.3-V or 2.5-V I/O
standards. 50-Ω on-chip series termination is available for 1.8- and 1.5-V
I/O standards (pending characterization).
Memory Interface IOE
Memory interface IOEs in HC210 and HC220 devices are located on the
top of the device. Memory interface IOEs in HC230 and HC240 devices
are located on the top and the bottom of the device. In Stratix II FPGAs,
the top and bottom IOEs support the memory interface IOE features.
The memory interface IOE has many features, including:
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The following I/O standards are supported when using the memory
interface IOEs and can be used to interface to external memory, including
DDR and DDR2 SDRAM, and QDRII, RLDRAM II, and SDR SRAM:
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1.8 V LVTTL/LVCMOS
1.5 V LVCMOS
Table 2–10. Programmable Drive Strength Support for General-Purpose
IOEs (Part 2 of 2)
Dedicated single-ended I/O buffers
3.3-V, 64-bit, 66 MHz PCI compliance
3.3-V, 64-bit, 133 MHz PCI-X 1.0 compliance
JTAG BST support
On-chip driver series termination
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Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Open-drain outputs
PCI clamping diode
DQ and DQS I/O pins
Double data rate (DDR) registers
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
REF
pins
I/O Standard
Programmable Drive Strength Options (mA)
2, 4, 6, 8
2, 4
Altera Corporation
September 2008