HC230F1020 Altera, HC230F1020 Datasheet - Page 149

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

## Example TimeQuest SDC Constraints Defining Clocks clk_a and clk_b
create_clock -period 10.0 -name clk_a [get_ports clk_a]
set_clock_latency -source -late 3.0 clk_a
set_clock_latency -source -early 2.0 clk_a
Altera Corporation
September 2008
f
The minimum set of timing constraints for a HardCopy II design are:
■
■
In addition, it is good design practice to develop timing constraints to
cover:
■
■
■
In TimeQuest, timing constraints are written in TimeQuest SDC format
and are read from an SDC file. An example file is demo_design.sdc. See
“Using TimeQuest” on page
In the Classic Timing Analyzer, timing constraints are applied using
dedicated Tcl commands and by assigning timing-specific attributes
using the set_instance_assignment command.
This section provides an overview of timing constraint development
using Tcl commands.
For more information on timing constraints, refer to the Timing Analysis
section in volume 3 of the Quartus II Handbook.
Specifying System Clocks
The most basic constraints that should be applied describe the clock for
each clock domain. Parameters usually specified for each clock are:
■
■
■
Clock uncertainty specified with the set_clock_uncertainty
command models any uncertainty in the clock period, including jitter,
and is often used to introduce some margin into the target clock
frequency. The following example constraints illustrate clock definition
for a design with two clock domains, clk_a and clk_b. In this case, both
clocks run at 100 MHz, but with different clock latency and skew.
Clock settings (F
Minimum and maximum delays for all I/O paths, including
asynchronous reset and control I/O signals
Specific cross-clock domain timing requirements
False paths
Multicycle paths
Clock period
Latency (LATE_CLOCK_LATENCY/EARLY_CLOCK_LATENCY
assignments)
Uncertainty (set_clock_uncertainty command)
MAX
) for each and every clock domain
6–30.
Assigning Timing Constraints
6–21