HC230F1020 Altera, HC230F1020 Datasheet - Page 104

no-image

HC230F1020

Manufacturer Part Number
HC230F1020
Description
Manufacturer
Altera
Datasheet

Specifications of HC230F1020

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HC230F1020
Manufacturer:
ALTERA
0
Part Number:
HC230F1020AJ
Manufacturer:
ALTERA
0
Part Number:
HC230F1020ANQ
Manufacturer:
Discera
Quantity:
2 000
Part Number:
HC230F1020AW
Manufacturer:
ALTERA
0
Part Number:
HC230F1020BA
Manufacturer:
ALTERA
0
Part Number:
HC230F1020BL
Manufacturer:
ALTERA
0
HardCopy Series Handbook, Volume 1
HardCopy II
Recommended
Settings in the
Quartus II
Software
5–12
The HardCopy II development flow involves additional planning and
preparation in the Quartus II software compared to a standard FPGA
design. This is because you are developing your design to be
implemented in two devices: a prototype of your design in a Stratix II
prototype FPGA, and a companion revision in a HardCopy II device for
production. You need additional settings and constraints to make the
Stratix II design compatible with the HardCopy II device and, in some
cases, you must remove certain settings in the design. This section
explains the additional settings and constraints necessary for your design
to be successful in both Stratix II FPGA and HardCopy II structured ASIC
devices.
Limit DSP and RAM to HardCopy II Device Resources
On the Assignments menu, click Settings to view the Settings dialog box.
In the Category list, select Device. In the Family list, select Stratix II.
Under Companion device, Limit DSP and RAM to HardCopy II device
resources is turned on by default
compatibility between the Stratix II and HardCopy II devices by ensuring
your design does not use resources in the Stratix II device that are not
available in the selected HardCopy II device.
1
Figure 5–7. Limit DSP and RAM to HardCopy II Device Resources Check Box
Enable Design Assistant to Run During Compile
You must use the Quartus II Design Assistant to check all HardCopy
series designs for design rule violations before submitting the designs to
the Altera HardCopy Design Center. Additionally, you must fix all critical
and high-level errors.
1
If you require additional memory blocks or DSP blocks for
debugging purposes using SignalTap
turn this setting off to compile and verify your design in your
test environment. However, your final Stratix II and
HardCopy II designs submitted to Altera for back-end
migration must be compiled with this setting turned on.
Altera recommends turning on the Design Assistant to run
automatically during each compile, so that during development,
you can see the violations you must fix.
(Figure
5–7). This maintains
®
II, you can temporarily
Altera Corporation
September 2008

Related parts for HC230F1020