HC230F1020 Altera, HC230F1020 Datasheet - Page 196

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
Figure 8–1. HardCopy II HC240 I/O Banks
Notes to
(1)
(2)
(3)
(4)
8–8
Figure 8–1
representation only. Refer to the pin list and Quartus II software for exact locations.
Differential HSTL and differential SSTL standards are available for bidirectional operations on DQS pin and input
only operations on PLL clock input pins; LVDS, LVPECL, and HyperTransport standards are available for input only
operations on PLL clock input pins. Refer to
HardCopy II devices and the Quartus II software does not support differential SSTL and differential HSTL
standards at left and right I/O banks. Side I/O banks do not have V
Figure 8–1
High-Speed IOEs
High-Speed IOEs
Figure
Bank 2
Bank 1
is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
shows the HC240 device. Other HardCopy II devices have fewer PLL blocks.
8–1:
PLL 1
PLL 2
PLL 7
PLL 8
Memory Interface IOEs
Memory Interface IOEs
I/O Banks 1 & 2 Support 3.3-,
2.5- & 1.8-V LVTTL/LVCMOS,
1.5-V LVCMOS, LVDS &
HyperTransport Technology
Bank 3
Bank 8
CLK, PLL_FB input pins SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST,
differential SSTL and differential HSTL I/O standards.
LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards.
LVDS & HyperTransport technology. CLK & PLL_FB
differential SSTL and differential HSTL I/O standards.
I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/
I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/
LVDS & HyperTransport technology. CLK & PLL_FB
LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V
pins support differential SSTL, differential HSTL,
pins support differential SSTL, differential HSTL,
HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards.
pins support LVPECL. DQS input pins support
pins support LVPECL. DQS input pins support
CLK, PLL_FB input pins & PLL_OUT output
“Differential I/O Termination” on page 8–20
Notes
Bank 12 Bank 10
Bank 11 Bank 9
PLL 12
PLL 11
& PLL_OUT output
(1), (2), (3),
PLL 5
PLL 6
I/O Banks 5 & 6 Support 3.3-,
2.5- & 1.8-V LVTTL/LVCMOS,
HyperTransport Technology
1.5-V LVCMOS, LVDS &
Memory Interface IOEs
Memory Interface IOEs
(4)
REF
Bank 4
Bank 7
pins.
PLL 10
PLL 4
PLL 3
PLL 9
for more details.
Altera Corporation
September 2008
Bank 5
High-Speed IOEs
Bank 6
High-Speed IOEs