DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 96

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
10.16.4 FIFO Information
The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO.
The count form this register informs the host as to how many bytes can be written into the transmit FIFO without
overflowing the buffer.
10.16.5
Receive Packet-Bytes Available
The lower 7 bits of the receive packet-bytes available register indicates the number of bytes (0 through 127) that
can be read from the receive FIFO. The value indicated by this register (lower seven bits) informs the host as to
how many bytes can be read from the receive FIFO without going past the end of a message. This value refers to
one of four possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a
complete packet. After reading the number of bytes indicated by this register, the host then checks the HDLC
information register for detailed message status.
If the value in the TR.HxRPBA register refers to the beginning portion of a message or continuation of a message,
then the MSB of the TR.HxRPBA register returns a value of 1. This indicates that the host can safely read the
number of bytes returned by the lower seven bits of the TR.HxRPBA register, but there is no need to check the
information register since the packet has not yet terminated (successfully or otherwise).
10.16.5.1 Receive HDLC Code Example
The following is an example of a receive HDLC routine:
1) Reset receive HDLC controller.
2) Set HDLC mode, mapping, and high watermark.
3) Start new message buffer.
4) Enable RPE and RHWM interrupts.
5) Wait for interrupt.
6) Disable RPE and RHWM interrupts.
7) Read TR.HxRPBA register. N = TR.HxRPBA (lower 7 bits are byte count, MSB is status).
8) Read (N and 7Fh) bytes from receive FIFO and store in message buffer.
9) Read TR.INFO5 register.
10) If PS2, PS1, PS0 = 000, then go to Step 4.
11) If PS2, PS1, PS0 = 001, then packet terminated OK, save present message buffer.
12) If PS2, PS1, PS0 = 010, then packet terminated with CRC error.
13) If PS2, PS1, PS0 = 011, then packet aborted.
14) If PS2, PS1, PS0 = 100, then FIFO overflowed.
15) Go to Step 3.
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