DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 172

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: SAPI Octet not equal to
LI.RX86S.SAPIHNE will generate an interrupt.
Bit 2: SAPI Octet not equal to
LI.RX86S.SAPILNE will generate an interrupt.
Bit 1: Control not equal to
generate an interrupt.
Bit 0: Address not equal to
generate an interrupt.
Bits 0 - 7: Transmit Queue Low Threshold (TQLT[0:7]) The transmit queue low threshold for the connection, in
increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to
determine the byte location of the threshold. Note that the transmit queue is for data that was received from the
Serial Interface to be sent to the Ethernet Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: Transmit Queue High Threshold (TQHT[0:7]) The transmit queue high threshold for the connection,
in increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to
determine the byte location of the threshold. Note that the transmit queue is for data that was received from the
Serial Interface to be sent to the Ethernet Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TQHT7
TQLT7
7
0
-
7
0
7
0
6
0
TQHT6
-
TQLT6
6
0
6
0
LI.TRX8C
LI.TRX86A
LI.RX86LSIE
Receive X.86 Interrupt Enable
123h
LI.TQLT
Serial Interface Transmit Queue Low Threshold (Watermark)
124h
LI.TQHT
Serial Interface Transmit Queue High Threshold (Watermark)
125h
5
0
-
LI.TRX86SAPIL
LI.TRX86SAPIH
TQHT5
TQLT5
5
0
5
0
Interrupt Enable (CNE3LIM) If this bit is set to 1, LI.RX86S.CNE will
Interrupt Enable (ANE4IM) If this bit is set to 1, LI.RX86S.ANE will
4
0
-
TQHT4
TQLT4
172 of 344
0
0
4
4
Interrupt Enable (SAPINEFEIM) If this bit is set to 1,
Interrupt Enable (SAPINE01IM) If this bit is set to 1,
SAPINE01IM
3
0
TQHT3
TQLT3
3
0
3
0
SAPINEFEIM
TQHT2
TQLT2
2
0
2
0
2
0
CNE3LI
TQHT1
TQLT1
M
1
0
1
0
1
0
ANE4IM
TQHT0
TQLT0
0
0
0
0
0
0