DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 3

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

10
9.15 E
9.16 BERT
9.17 T
9.18 R
9.19 X.86 E
9.20 C
10.1 T1/E1/J1 C
10.2 P
10.3 T1/E1/J1 T
10.4 T1 F
10.5 E1 F
10.6 P
10.7 E
10.8 DS0 M
10.9 S
10.10 P
10.11 C
10.12 E
10.13 G.706 I
10.14 T1 B
10.15 R
10.16 A
10.17 A
9.14.1 DTE and DCE Mode .............................................................................................................................58
9.15.1 MII Mode Options..................................................................................................................................61
9.15.2 RMII Mode.............................................................................................................................................61
9.15.3 PHY MII Management Block and MDIO Interface ................................................................................62
9.16.1 Receive Data Interface .........................................................................................................................63
9.16.2 Repetitive Pattern Synchronization.......................................................................................................64
9.16.3 Pattern Monitoring.................................................................................................................................64
9.16.4 Pattern Generation................................................................................................................................64
INTEGRATED T1/E1/J1 TRANSCEIVER ........................................................................................ 72
10.4.1 T1 Transmit Transparency....................................................................................................................74
10.4.2 AIS-CI and RAI-CI Generation and Detection ......................................................................................74
10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation..............................................................................75
10.5.1 Automatic Alarm Generation.................................................................................................................77
10.7.1 Line-Code Violation Counter (TR.LCVCR) ...........................................................................................78
10.7.2 Path Code Violation Count Register (TR.PCVCR) ...............................................................................79
10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) ..............................................................................80
10.7.4 E-Bit Counter (TR.EBCR) .....................................................................................................................80
10.9.1 Processor-Based Receive Signaling ....................................................................................................82
10.9.2 Hardware-Based Receive Signaling .....................................................................................................83
10.9.3 Processor-Based Transmit Signaling ...................................................................................................84
10.9.4 Hardware-Based Transmit Signaling ....................................................................................................85
10.10.1 Idle-Code Programming Examples .......................................................................................................87
10.12.1 Receive Elastic Store............................................................................................................................88
10.12.2 Transmit Elastic Store ...........................................................................................................................89
10.12.3 Elastic Stores Initialization ....................................................................................................................89
10.12.4 Minimum Delay Mode ...........................................................................................................................89
10.14.1 Transmit BOC .......................................................................................................................................91
10.16.1 Method 1: Internal Register Scheme Based on Double-Frame............................................................92
10.16.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe .......................................................92
10.17.1 HDLC Configuration..............................................................................................................................93
10.17.2 FIFO Control .........................................................................................................................................95
10.17.3 HDLC Mapping......................................................................................................................................95
RANSMIT
THERNET
ER
ER
RROR
IGNALING
ER
LASTIC
DDITIONAL
DDITIONAL
ECEIVE
OMMITTED
HANNEL
ECEIVE
-C
-C
-C
RAMER
RAMER
IT
HANNEL
HANNEL
HANNEL
-O
IN THE
NCODING AND
ONITORING
NTERMEDIATE
C
S
P
RIENTED
BOC .............................................................................................................................. 91
OUNTERS
B
TORES
P
ACKET
MAC ........................................................................................................................... 59
O
RANSCEIVER
LOCKING
LOCKS
/F
/F
ACKET
(S
HDLC C
I
PERATION
NFORMATION
E
ORMATTER
ORMATTER
A
O
L
I
THERNET
DLE
)
OOPBACK
PERATION
AND
O
P
C
F
........................................................................................................................ 72
........................................................................................................................ 78
P
ROCESSOR
PERATION
C
ODE
UNCTION
ROCESSOR
R
ONTROLLERS IN
D
ODE
CRC-4 U
I
EGISTERS
NTERNATIONAL
ECODING
................................................................................................................. 82
I
(BOC) C
M
NTERRUPTS
C
C
............................................................................................................. 77
G
R
............................................................................................................ 73
APPER
ONTROL AND
ONTROL AND
ENERATION
ATE
........................................................................................................ 81
........................................................................................................ 88
...................................................................................................... 66
PDATING
.................................................................................................... 65
.................................................................................................... 68
C
................................................................................................... 88
ONTROLLER
................................................................................................. 62
ONTROLLER
T1/E1/J1 T
............................................................................................ 73
(S
........................................................................................ 86
S
S
I
(E1 M
) B
TATUS
TATUS
3 of 344
IT
............................................................................... 91
.............................................................................. 71
O
ODE
PERATION
........................................................................... 74
........................................................................... 76
RANSCEIVER
O
NLY
)............................................................ 90
(E1 O
....................................................... 93
NLY
)........................................... 92