DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 212

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 4 - 7: Device ID (ID4 to ID7). The upper four bits of TR.IDR are used to display the transceiver ID.
Bits 0 – 3: Chip Revision Bits (ID0 to ID3). The lower four bits of TR.IDR are used to display the die revision of
the chip. IDO is the LSB of a decimal code that represents the chip revision.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive Pulse-Density Violation Event (RPDV). Set when the receive data stream does not meet the
ANSI T1.403 requirements for pulse density.
Bit 6: Transmit Pulse-Density Violation Event (TPDV). Set when the transmit data stream does not meet the
ANSI T1.403 requirements for pulse density.
Bit 5: Change-of-Frame Alignment Event (COFA). Set when the last resync resulted in a change-of-frame or
multiframe alignment.
Bit 4: Eight Zero-Detect Event (8ZD). Set when a string of at least eight consecutive 0s (regardless of the length
of the string) have been received at RPOSI and RNEGI.
Bit 3: Sixteen Zero-Detect Event (16ZD). Set when a string of at least 16 consecutive 0s (regardless of the length
of the string) have been received at RPOSI and RNEGI.
Bit 2: Severely Errored Framing Event (SEFE). Set when two out of six framing bits (Ft or FPS) are received in
error.
Bit 1: B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RPOS and RNEG
independent of whether the B8ZS mode is selected or not by TR.T1TCR2.7. Useful for automatically setting the
line coding.
Bit 0: Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error.
RPDV
ID7
7
1
7
0
TR.IDR
Device Identification Register
0Fh
TR.INFO1
Information Register 1
10h
TPDV
ID6
6
0
6
0
COFA
ID5
5
1
5
0
212 of 344
8ZD
ID4
4
1
4
0
16ZD
ID3
X
3
3
0
SEFE
ID2
X
2
2
0
B8ZS
ID1
X
1
1
0
FBE
ID0
X
0
0
0