DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 46

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

9.2 Resets and Low Power Modes
The external RST pin and the global reset bit in
signal resets the status and control registers on the chip (except the GL.CR1.RST bit) to their default values and
resets all the other flops to their reset values. The processor bus output signals are also placed in high-impedance
mode when the RST pin is active (low). The global reset bit (GL.CR1.RST) stays set after a one is written to it, but
is reset to zero when the external RST pin is active or when a zero is written to it. Allow 5ms after initiating a reset
condition for the reset operation to complete.
The Serial Interface reset bit in
default values, except for the LI.RSTPD.RST bit. The serial interface includes the HDLC encoder/decoder, X86
encoder and decoder and the corresponding serial port. The serial interface reset bit (LI.RSTPD.RST) stays set
after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it.
Table 9-2. Reset Functions
Hardware Device Reset
Hardware JTAG Reset
Global Software Reset
Serial Interface Reset
Queue Pointer Reset
There are several features in the DS33R11 to reduce power consumption. The reset bit in the
minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1.RST bit may be held in reset
indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization and
configuration. For the lowest possible standby current, clocks may be externally gated.
The T1/E1/J1 transceiver contains an on-chip power-up reset function that automatically clears the writeable
register space immediately after power is supplied to the transceiver. The user can issue a chip reset at any time.
Issuing a reset disrupts traffic flowing through the transceiver until the device is reprogrammed. The reset can be
issued through hardware using the TSTRST pin or through software using the SFTRST function in the master
mode register. The LIRST (TR.LIC2.6) should be toggled from 0 to 1 to reset the line interface circuitry. (It takes
the transceiver about 40ms to recover from the LIRST bit being toggled.) Finally, after the TSYSCLK and
RSYSCLK inputs are stable, the receive and transmit elastic stores should be reset (this step can be skipped if the
elastic stores are disabled).
RESET FUNCTION
LI.RSTPD
LOCATION
GL.C1QPR
JTRST Pin
LI.RSTPD
GL.CR1
RST Pin
resets all the status and control registers on the serial interface to their
GL.CR1
Transition from a logic 0 to a logic 1 resets the device.
Resets the JTAG test port.
Writing to this bit resets the device.
Writing to this bit resets the Serial Interface.
Writing to this bit resets the Queue Pointers.
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create an internal global reset signal. The global reset
COMMENTS
LI.RSTPD
register