DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 4

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

11
12
10.18 L
10.19 D4/SLC-96 O
10.20 P
10.21 L
10.22 MCLK P
10.23 J
10.24 CMI (C
10.25 R
10.26 T1/E1/J1 TRANSCEIVER BERT FUNCTION ........................................................................... 108
10.27 P
10.28 P
10.29 F
10.30 T1/E1/J1 T
11.1 R
11.2 G
11.3 A
11.4 BERT R
11.5 S
11.6 E
11.7 T1/E1/J1 T
12.1 F
12.2 MII
12.3 T
10.17.4 FIFO Information ...................................................................................................................................96
10.17.5 Receive Packet-Bytes Available ...........................................................................................................96
10.18.1 Overview ...............................................................................................................................................97
10.18.2 Receive Section ....................................................................................................................................97
10.18.3 Transmit Section ...................................................................................................................................98
10.21.1 LIU Operation......................................................................................................................................100
10.21.2 Receiver ..............................................................................................................................................100
10.21.3 Transmitter ..........................................................................................................................................102
10.26.1 BERT Status .......................................................................................................................................108
10.26.2 BERT Mapping....................................................................................................................................108
10.26.3 BERT Repetitive Pattern Set ..............................................................................................................110
10.26.4 BERT Bit Counter................................................................................................................................110
10.26.5 BERT Error Counter............................................................................................................................110
10.26.6 BERT Alternating Word-Count Rate ...................................................................................................110
10.27.1 Number-of-Errors Registers................................................................................................................111
DEVICE REGISTERS..................................................................................................................... 117
11.1.1 Global Ethernet Mapper Register Bit Map ..........................................................................................118
11.1.2 Arbiter Register Bit Map ......................................................................................................................119
11.1.3 BERT Register Bit Map .......................................................................................................................119
11.1.4 Serial Interface Register Bit Map ........................................................................................................120
11.1.5 Ethernet Interface Register Bit Map....................................................................................................122
11.1.6 MAC Register Bit Map ........................................................................................................................123
11.3.1 Arbiter Register Bit Descriptions .........................................................................................................143
11.5.1 Serial Interface Transmit and Common Registers..............................................................................151
11.5.2 Serial Interface Transmit Register Bit Descriptions ............................................................................151
11.5.3 Transmit HDLC Processor Registers..................................................................................................152
11.5.4 X.86 Registers.....................................................................................................................................159
11.5.5 Receive Serial Interface......................................................................................................................161
11.6.1 Ethernet Interface Register Bit Descriptions.......................................................................................174
11.6.2 MAC Registers ....................................................................................................................................186
11.7.1 Number-of-Errors Left Register...........................................................................................................299
FUNCTIONAL TIMING ................................................................................................................... 300
ITTER
EGACY
INE
RACTIONAL
UNCTIONAL
RANSCEIVER
ROGRAMMABLE
AYLOAD
ROGRAMMABLE
RBITER
ERIAL
THERNET
ECOMMENDED
EGISTER
LOBAL
AND
I
NTERFACE
A
ODE
I
NTERFACE
R
RMII I
FDL S
EGISTERS
RESCALER
TTENUATOR
R
E
EGISTER
B
EGISTERS
I
RROR
RANSMIT
RANSCEIVER
NTERFACE
M
IT
T1/E1 S
S
PERATION
ARK
T1 M
M
ERIAL
NTERFACES
UPPORT
C
APS
U
-I
I
B
N
IRCUITS
NIT
I
NSERTION
ACKPLANE
...................................................................................................................... 144
-B
NVERSION
D
R
..................................................................................................................... 103
ODE
F
I/O T
................................................................................................................... 103
................................................................................................................... 118
................................................................................................................... 143
EGISTERS
EFINITIONS FOR
UPPORT
AND
(LIU)......................................................................................................... 100
LOW
R
(T1 M
................................................................................................................ 98
EGISTERS
R
F
IMING
UNCTIONAL
........................................................................................................... 104
EGISTERS
L
.......................................................................................................... 301
D
OOP
IAGRAMS
F
) O
C
ODE
..................................................................................................... 112
UNCTION
.................................................................................................... 151
LOCK
.................................................................................................. 300
C
PTION
) ............................................................................................... 97
ODE
.............................................................................................. 174
........................................................................................... 201
E
S
T
......................................................................................... 113
THERNET
........................................................................................ 103
YNTHESIZER
G
IMING
(T1 M
ENERATION AND
4 of 344
.............................................................................. 303
ODE
M
APPER
O
..................................................................... 112
NLY
) ........................................................... 111
............................................................ 134
D
ETECTION
............................................ 99