DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 152

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Queue Loopback Enable (QLP) If this bit set to 1, data received on the Serial Interface is looped back to
the Serial Interface transmitter. Received data will not be sent from the Serial Interface to the Ethernet Interface.
Buffered packet data will remain in queue until the loopback is removed.
11.5.1.2 Transmit HDLC Processor Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The user should take care not to modify this register value during packet error insertion.
Bits 5 - 6: Transmit FCS Append Disable (TFAD) – This bit controls whether or not an FCS is appended to the
end of each packet. When equal to 0, the calculated FCS bytes are appended to packets. When set to 1, packets
are transmitted without FCS. In X.86 Mode, FCS is always 32 bits and is always appended to the packet.
Bit 4: Transmit FCS-16 Enable (TF16) – When 0, the FCS processing uses a 32-bit FCS. When 1, the FCS
processing uses a 16-bit FCS. In X.86 Mode, 32-bit FCS processing is always enabled, regardless of this bit.
Bit 3: Transmit Bit Synchronous Inter-frame Fill Value (TIFV) – When 0, inter-frame fill is done with the flag
sequence (7Eh). When 1, inter-frame fill is done with all '1's (FFh). This bit is ignored in X.86 mode and the
interframe flag is always 7E.
Bit 2: Transmit Scrambling Disable (TSD) – When equal to 0, X
scrambling is disabled.
Bit 1: Transmit Bit Reordering Enable (TBRE) – When equal to 0, bit reordering is disabled (The first bit
transmitted is from the MSB of the transmit FIFO byte TFD [7]). When set to 1, bit reordering is enabled (The first
bit transmitted is from the LSB of the transmit FIFO byte TFD [0]).
Bit 0: Transmit Initiate Automatic Error Insertion (TIAEI) – This write-only bit initiates error insertion. See the
LI.TEPHC register definition for details of usage.
7
0
7
0
-
-
6
0
6
0
-
-
LI.LPBK
Serial Interface Loopback Control Register
0C2h
LI.TPPCL
Transmit Packet Processor Control Low Register
0C4h
TFAD
5
0
5
0
-
152 of 344
TF16
0
0
4
4
-
TIFV
3
0
3
0
-
43
+1 scrambling is performed. When set to 1,
TSD
2
0
2
0
-
TBRE
1
0
1
0
-
TIAEI
QLP
0
0
0
0