DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 187

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission of a collided packet even after the
collision period. When this bit is clear, retransmission of late collisions is disabled.
Bit 10: Disable Retry (DRTY) When set to 1, the MAC makes only a single attempt to transmit each frame. If a
collision occurs, the MAC ignores the current frame and proceeds to the next frame. When this bit equals 0, the
MAC will retry collided packets 16 times before signaling a retry error.
Bit 8: Automatic Pad Stripping (ASTP) When set to 1, all incoming frames with less than 46 byte length are
automatically stripped of the pad characters and FCS.
Bits 6 - 7: Back-Off Limit (BOLMT[0:1]) These two bits allow the user to set the back-off limit used for the
maximum retransmission delay for collided packets. Default operation limits the maximum delay for retransmission
to a countdown of 10 bits from a random number generator. The user can reduce the maximum number of counter
bits as described in the table below. See IEEE 802.3 for details of the back-off algorithm.
Bit 7
Bit 5: Deferral Check (DC) When set to 1, the MAC will abort packet transmission if it has deferred for more than
24,288 bit times. The deferral counter starts when the transmitter is ready to transmit a packet, but is prevented
from transmission because CRS is active. If the MAC begins transmission but a collision occurs after the beginning
of transmission, the deferral counter is reset again. If this bit is equal to zero, then the MAC will defer indefinitely.
Bit 3: Transmitter Enable (TE) When set to 1, packet transmission is enabled. When equal to zero, transmission
is disabled.
Bit 2: Receiver Enable (RE) When set to 1, packet reception is enabled. When equal to zero, packets are not
received.
0
0
1
1
Bit 6
0
1
0
1
Random Number Generator Bits Used
10
8
4
1
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