PIC18F452-I/LG Microchip Technology, PIC18F452-I/LG Datasheet - Page 97

• Manufacturer Part Number: PIC18F452-I/LG
• Description: IC MCU FLASH 16KX16 W/AD 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-I/LG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• For Use With: XLT44L2 - SOCKET TRAN ICE 44PLCCDVA16XL441 - ADAPTER DEVICE ICE 44PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4
This section is applicable only to the PIC18F4X2
devices.
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISD bit (= 0) will
make the corresponding PORTD pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register reads and writes the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL. See Section 9.6 for additional information on
the Parallel Slave Port (PSP).
EXAMPLE 9-4:
© 2006 Microchip Technology Inc.
Note:
CLRF
CLRF
MOVLW 0xCF
MOVWF TRISD
PORTD, TRISD and LATD
Registers
On a Power-on Reset, these pins are
configured as digital inputs.
PORTD
LATD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
INITIALIZING PORTD
FIGURE 9-8:
WR TRISD
WR LATD
or
PORTD
Note 1:
Data
Bus
RD PORTD
I/O pins have diode protection to V
TRIS Latch
Data Latch
RD LATD
D
D
CK
CK
RD TRISD
Q
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
Q
PIC18FXX2
Q
EN
EN
Schmitt
Trigger
Input
Buffer
D
DS39564C-page 95
DD
and V
I/O pin
SS
.
(1)