ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 92

• Manufacturer Part Number: ATA6616-P3QW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.10.2.2
4.10.2.3
Figure 4-26. Break Before Make, Switching between Input and Output
92
SYSTEM CLOCK
INSTRUCTIONS
Atmel ATA6616/ATA6617
Toggling the Pin
Break-Before-Make Switching
PORTx
DDRx
R 16
R 17
Px0
Px1
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has
to be configured as an output pin. The port pins are tri-stated when reset condition becomes
active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin,
the port pin is driven low (zero).
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI assembler instruction can be used to toggle one single bit in a port.
In the Break-Before-Make mode when switching the DDRxn bit from input to output an imme-
diate tri-state period lasting one system clock cycle is introduced as indicated in
For example, if the system clock is 4MHz and the DDRxn is written to make an output, the
immediate tri-state period of 250ns is introduced, before the value of PORTxn is seen on the
port pin. To avoid glitches it is recommended that the maximum DDRxn toggle frequency is
two system clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the
port-wise BBMx enable bits. For further information about the BBMx bits, see
Register – PORTCR” on page
no immediate tri-state period introduced.
out DDRx, r16
0x01
tri-state
immediate tri-state cycle
0x02
0x01
0x55
0x02
nop
99. When switching the DDRxn bit from output to input there is
tri-state
out DDRx, r17
immediate tri-state cycle
0x01
tri-state
9132D–AUTO–12/10
“Port Control
Figure
4-26.