ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 131

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ATA6616-P3QW

Manufacturer Part Number
ATA6616-P3QW
Description
TXRX MULTICHIP MOD LIN SIP 38QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6616-P3QW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL
Quantity:
950
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
9132D–AUTO–12/10
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from an edge has been applied to the T1 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
tor uses sampling, the maximum frequency of an external clock it can detect is half the
sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capaci-
tors) tolerances, it is recommended that maximum frequency of an external clock source is
less than f
An external clock source can not be prescaled.
Figure 4-43. Prescaler for Timer/Counter1
Note:
CLK
PSRn
1. The synchronization logic on the input pin (T1) is shown in
Tn
I/O
clk_I/O
/2.5.
Synchronization
ExtClk
< f
CSn0
CSn1
CSn2
clk_I/O
/2) given a 50/50 % duty cycle. Since the edge detec-
Clear
(1)
Atmel ATA6616/ATA6617
TIMER/COUNTERn CLOCK SOURCE
0
10-BIT T/C PRESCALER
clk
Tn
Figure
4-42.
131

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