ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 38

• Manufacturer Part Number: ATA6616-P3QW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.7.2
38
Atmel ATA6616/ATA6617
Interrupt Response Time
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
The interrupt execution response for all the enabled AVR
mum. After four clock cycles the Program Vector address for the actual interrupt handling
routine is executed. During this four clock cycle period, the Program Counter is pushed onto
the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three
clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction
is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep
mode, the interrupt execution response time is increased by four clock cycles. This increase
comes in addition to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
Assembly Code Example
C Code Example
Assembly Code Example
C Code Example
in
cli
sbi
sbi
out
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
sei
sleep
; note: will enter sleep before any pending
; interrupt(s)
_SEI();
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
r16, SREG
EECR, EEMPE
EECR, EEPE
SREG, r16
; disable interrupts during timed sequence
; set Global Interrupt Enable
; enter sleep, waiting for interrupt
/* set Global Interrupt Enable */
; store SREG value
; start EEPROM write
; restore SREG value (I-bit)
®
interrupts is four clock cycles mini-
9132D–AUTO–12/10