ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 88

• Manufacturer Part Number: ATA6616-P3QW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9.3.3
4.9.3.4
88
Atmel ATA6616/ATA6617
External Interrupt Flag Register – EIFR
Pin Change Interrupt Control Register – PCICR
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel
• Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes
set (one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 is configured as a level interrupt.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes
set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel ATtiny87/167, and will always read as zero.
• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
Read/Write
Initial Value
Read/Write
Initial Value
Bit
Bit
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
®
ATtiny87/167, and will always read as zero.
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
R
R
2
–
0
2
–
0
PCIE1
INTF1
R/W
R/W
1
0
1
0
PCIE0
INTF0
R/W
R/W
9132D–AUTO–12/10
0
0
0
0
PCICR
EIFR