ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 197

• Manufacturer Part Number: ATA6616-P3QW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9132D–AUTO–12/10
Re-synchronization in LIN Mode
When waiting for Rx Header, LBT[5..0] = 32 in LINBTR register. The re-synchronization
begins when the BREAK is detected. If the BREAK size is not in the range (10.5 bits min., 28
bits max. — 13 bits nominal), the BREAK is refused. The re-synchronization is done by adjust-
ing LBT[5..0] value to the SYNCH field of the received header (0x55). Then the PROTECTED
IDENTIFIER is sampled using the new value of LBT[5..0]. The re-synchronization imple-
mented in the controller tolerates a clock deviation of ± 20% and adjusts the baud rate in a
±2% range.
The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be
reset to 32 for the next header.
The LINBTR register can be used to (software) re-calibrate the clock oscillator.
The re-synchronization is not performed if the LIN node is enabled as a master.
Handling LBT[5..0]
LDISR bit of LINBTR register is used to:
Note that the LENA bit of LINCR register is important for this handling (see
page
Figure 4-75. Handling LBT[5..0]
• Disable the re-synchronization (for instance in the case of LIN MASTER node),
• To enable the setting of LBT[5..0] (to manually adjust the baud rate especially in the case of
UART mode). A minimum of 8 is required for LBT[5..0] due to the sampling operation.
197).
=1
Write in LINBTR register
(LINCR bit 4)
LENA ?
Enable re-synch. in LIN mode
LBT[5..0] forced to 0x20
LDISR forced to 0
=0
LDISR
to write
=0
Atmel ATA6616/ATA6617
=1
Disable re-synch. in LIN mode
LBT[5..0] = LBT[5..0] to write
LDISR forced to 1
(LBT[5..0]
min
=8)
Figure 4-75 on
197