ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 173

• Manufacturer Part Number: ATA6616-P3QW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.15
4.15.1
4.15.2
9132D–AUTO–12/10
USI – Universal Serial Interface
Features
Overview
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The Universal Serial Interface, or USI, provides the basic hardware resources needed for
serial communication. Combined with a minimum of control software, the USI allows signifi-
cantly higher transfer rates and uses less code space than solutions based on software only.
Interrupts are included to minimize the processor load.
A simplified block diagram of the USI is shown on
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the
Figure 4-62. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register is directly accessible via the data bus and contains the incoming
and outgoing data. The register has no buffering so the data must be read as quickly as possi-
ble to ensure that no data is lost. The USI Data Register is a serial shift register and the most
significant bit that is the output of the serial shift register is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the USI
Data Register Output and output pin, which delays the change of data output to the opposite
clock edge of the data input sampling. The serial input is always sampled from the Data Input
(DI) pin independent of the configuration.
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
USIDR
USIDB
USISR
USICR
2
4-bit Counter
“Register Descriptions” on page
3
2
1
0
3
2
1
0
D Q
LE
[1]
Atmel ATA6616/ATA6617
TIM0 COMP
0
1
Figure
4-62. CPU accessible I/O Registers,
181.
Two-wire Clock
Control Unit
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
(Output only)
(Input/Open Drain)
(Input/Open Drain)
173