ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 143

• Manufacturer Part Number: ATA6616-P3QW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9132D–AUTO–12/10
Figure 4-47. Output Compare Unit, Block Diagram
The OCR1A/B Register is double buffered when using any of the twelve Pulse Width Modula-
tion (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR1A/B Compare Register to either TOP or BOTTOM of the counting sequence. The syn-
chronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR1A/B Register access may seem complex, but this is not case. When the double
buffering is enabled, the CPU has access to the OCR1A/B Buffer Register, and if double buff-
ering is disabled the CPU will access the OCR1A/B directly. The content of the OCR1A/B
(Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does
not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1A/B
is not read via the high byte temporary register (TEMP). However, it is a good practice to read
the low byte first as when accessing other 16-bit registers. Writing the OCR1A/B Registers
must be done via the TEMP Register since the compare of all 16 bits is done continuously.
The high byte (OCR1A/BH) has to be written first. When the high byte I/O location is written by
the CPU, the TEMP Register will be updated by the value written. Then when the low byte
(OCR1A/BL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits
of either the OCR1A/B buffer or OCR1A/B Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to
on page
136.
OCRnxH Buf.(8-bit)
OCRnxH (8-bit)
BOTTOM
OCRnx Buffer (16-bit Register)
TEMP (8-bit)
TOP
OCRnx (16-bit Register)
OCRnxL Buf.(8-bit)
OCRnxL (8-bit)
DATA BUS
Atmel ATA6616/ATA6617
Waveform Generator
WGMn3:0
=
(16-bit Comparator )
(8-bit)
COMnx1:0
TCNTnH (8-bit)
OCFnx
“Accessing 16-bit Registers”
TCNTn (16-bit Counter)
(Int.Req.)
TCNTnL (8-bit)
OCnxW
OCnxX
OCnxU
OCnxV
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