ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 49

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ATA6616-P3QW

Manufacturer Part Number
ATA6616-P3QW
Description
TXRX MULTICHIP MOD LIN SIP 38QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6616-P3QW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL
Quantity:
950
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
4.5.1.1
4.5.1.2
4.5.1.3
4.5.1.4
4.5.1.5
4.5.2
9132D–AUTO–12/10
Clock Sources
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
Asynchronous Timer Clock – clk
ADC Clock – clk
I/O
The CPU clock is routed to parts of the system concerned with the AVR
Examples of such modules are the General Purpose Register File, the Status Register and the
Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from perform-
ing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like synchronous Timer/Counter. The
I/O clock is also used by the External Interrupt module, but note that some external interrupts
are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active
simultaneously with the CPU clock.
The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly
from an external clock or an external low frequency crystal. The dedicated clock domain
allows using this Timer/Counter as a real-time counter even when the device is in sleep mode.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O
clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC
conversion results.
The device has the following clock source options, selectable by Flash Fuse bits (default) or
by the CLKSELR register (dynamic clock switch circuit) as shown below. The clock from the
selected source is input to the AVR
Table 4-5.
The various choices for each clocking option are given in the following sections.
Device Clocking Option
External Clock
Calibrated Internal RC Oscillator 8.0MHz
Watchdog Oscillator 128kHz
External Low-frequency Oscillator
External Crystal/Ceramic Resonator (0.4 - 0.9MHz)
External Crystal/Ceramic Resonator (0.9 - 3.0MHz)
External Crystal/Ceramic Resonator (3.0 - 8.0MHz)
External Crystal/Ceramic Resonator (8.0 - 16.0MHz)
Notes:
CPU
ADC
FLASH
1. For all fuses “1” means unprogrammed while “0” means programmed
2. Flash Fuse bits
3. CLKSELR register bits
Device Clocking Options Select
ASY
®
clock generator, and routed to the appropriate modules.
Atmel ATA6616/ATA6617
(1)
versus PB4 and PB5 Functionality
CKSEL3..0
CSEL3..0
0000
0010
0011
100x
101x
110x
01xx
111x
b
b
b
b
b
b
b
b
(3)
(2)
XTAL1
XTAL1
XTAL1
XTAL1
XTAL1
CLKI
PB4
I/O
I/O
®
core operation.
CLKO - I/O
CLKO - I/O
CLKO - I/O
XTAL2
XTAL2
XTAL2
XTAL2
XTAL2
PB5
49

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