HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 52

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 7: Image Sensor Camera Interface
52
MHz. Normally, the camera output serial data includes 8 data bits plus HSYNC and
VSYNC, plus a START and STOP bit. Optionally, the output can be configured to include
10-bit data, with HSYNC and VSYNC encoded into the video data. Refer to the Micron
MT9V022 data sheet for more details on configuration modes.
The timing relationship between the clock and data is not specified, nor is the maximum
cable rate. This requires the FPGA receiver to have the ability to adjust or skew the camera
clock phase to clock in valid camera data. This is shown in
www.xilinx.com
MT9V022
Figure 7-2: Camera Clock
SHFT_CLK_OUT
SER_DATA_OUT
XCV2P4 FPGA
Clock Delay
Video Input/Output Daughter Card
dly
UG235 (v1.2.1) October 31, 2007
Figure
ug235_ch6_02_120805
7-1.
R