HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 28

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 3: Component and S-Video Interfaces
28
Analog Output Signal Conditioning
ADV7403 Configuration Modes
Output analog signals are first conditioned to meet standards requirements and then
connected to the red, green and blue RCA type connectors X2, X4 and X6 respectively.
Analog output is conditioned by a combination of passive and active circuits, as illustrated
in
Refer to the ADV7403 data sheet for details configuring the ADV7403 device.
The ADV7403 is mapped to I2C address 0x40/0x41.
Table 3-1: Configuration Modes for ADV7403 Video Decoder Chip
525P
Primary
Mode
Video
Standard
Enable
XTAL
ADC Power
and PLL
Bias Control
TLLC
Control
ADC sw1
ADC sw2
Figure
Register
Name
3-3.
Register
Address
0x1D
0x05
0x06
0x3a
0x3b
0x6b
0x85
0x86
0xb3
0x0e
0x52
0x54
0x0e
0x3c
0xc3
0xc4
www.xilinx.com
Register
Value
0xC2
0x01
0x08
0x47
0x10
0x80
0x18
0x0b
0x54
0x86
0x80
0x46
0x00
0x00
0x5c
0xfe
[2:0] =PRIM_MODE
[3:0]= VID_STD
latch clock = 13-55 MHz
External Bias Enable'
PLL qpump
[3:0]cpop_sel(1=20-bit,2=30-bit)
Turn off SSPD as sync is on Y
ENABLE SDTI line count mode
SDTI
[7:4]=adc1
[3:0]=adc0
[7]=sw_en,
[6]=SOG
[3:0]=adc2
Startup sequence
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
Description
R