HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 20

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 2: VIODC to ML402 Card Interface
VIOBUS Signal Definitions
Table 2-1: VIOBUS Signal Definitions
20
VIO Data Bus (a moderate-speed single-ended bus)
vio_up[25:0]
vio_up_ena
vio_dn[25:0]
vio_dn_ena
Sport Serial Bus (used to configure registers in the VIODC FPGA)
vio_sport_up
vio_sport_dn
vio_sport_sync
vio_sport_clk
I2C Serial Bus (used to configure registers in the video devices)
vio_i2c_sda_up
vio_i2c_sda_dn
vio_i2c_scl_up
Miscellaneous
vio_reset
Clock
vio_up_clk_lvds_P,N
Signal
Refer to the VIOBUS pinout in
Data bus to the VIODC
Pixel enable for
vio_up[25:0]
Data bus from the VIODC
vio_up[25:0]
data, 16-bit address)
I2C write data
I2C return data
I2C clock signal
Active High reset to
VIODC
Pixel enable for
Sport return data
Sport sync pulse
Sport clock
Sport write data (16-bit
Description
www.xilinx.com
nbits
Appendix A, “Reference Information”
26
26
1
1
1
1
1
1
1
1
1
1
1
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVDS25
Type
400 MHz
100 MHz
100 Mhz
100 MHz
100 MHz
10 MHz
10 MHz
10 MHz
10 MHz
400 kHz
400 kHz
400 kHz
10 MHz
Target
Speed
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
ML402
ML402
VIODC
VIODC
ML402
VIODC
ML402
ML402
ML402
VIODC
ML402
ML402
ML402
Source
FPGA
for signal locations.
hdr1[20:2],
hdr2[2:32]
hdr1[22]
hdr1[42:24],
hdr2[64:34]
hdr1[44]
hdr1[54]
hdr1[52]
hdr1[50]
hdr1[48]
hdr1[60]
hdr1[58]
hdr1[56]
hdr1[46]
hdr1[64:62]]
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