HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 48

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 6: SDI Interface
SDI Transmitter
48
switches
ML402
ICS664-02
from
DIP
freq control
BUFG
Generator
Generator
Table 6-5:
Figure 6-3
provides either 74.25 MHz or 74.1758 MHz in HD mode or 54 MHz in SD mode. This
reference clock is connected directly to the REFCLK input of the RocketIO transceiver and
also buffered by a global clock buffer and distributed as the transmitter clock to all portions
of the transmitter section.
Pattern
Pattern
The HD pattern generator produces four different video patterns for each of the eight HD
video formats supported. The video pattern and format is selected either by the DIP
switches on the VIODC or by the ML402 board. The HD pattern generator also produces
an 11-bit line number value. The line number is inserted into the video stream after each
End of Active Video (EAV) by the line number insertion logic. The Cyclic Redundancy
Check (CRC) block generates CRCs for both the Y and C channels and inserts them into the
video stream after the line number. Finally, the video is encoded for transmission by the
HD-SDI scrambler and provided to the RocketIO transceiver where it is serialized and sent
as an HD-SDI bitstream.
In SD mode, the clock from the ICS664-02 runs at 54 MHz. This is supplied to the RocketIO
transceiver where it is multiplied by 20, so that the actual data rate of the transceiver’s
output is 1.08 Gb/s or 4X the 270 Mb/s SD-SDI bit rate. The SD pattern generator and the
other elements of the SD-SDI transmitter data path need to run at 27 MHz, so a clock
enable, asserted every other clock cycle, is generated and distributed to all elements of the
SD-SDI transmitter data path.
The SD pattern generator produces either National Television System Committee (NTSC) or
Phase Alternating Line ( PAL) component 4:2:2 video. The EDH processor calculates the
SD Fsc 2
SD Fsc 3
HD
SD
Register
Name
HD mode: 74.25 MHz or74.1578 MHz
SD mode: 54 MHz
Generator
Enable
Clock
line
num
Y
C
Figure 6-3: SDI Transmitter Block Diagram
is a block diagram of the SDI transmitter. The ICS664-02 frequency synthesizer
10
10
11
10
ADV7321B Register Settings for PAL (Continued)
Processor
Insertion
Number
EDH
Line
Address
0x4E
0x4F
10
10
10
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Scrambler
Insertion
SD-SDI
CRC
Value
0x2A
0x09
10
10
10
Scrambler
Replicate
HD-SDI
4X Bit
20
20
hd_sd
20
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
TXUSRCLK
TXUSRCLK2
TXDATA
REFCLK
Description
RocketIO
TXP
TXN
SDI Cable
Driver SDI Out
ug235_ch5_03_111405
R