HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 39

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Table 4-3: Analog XGA60
Table 4-4: Analog SXGA60
Table 4-5: Analog UXGA60
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
Active Interface
PLL Div MSB
PLL Div LSB
VCO/CPMP
Phase Adjust
Clamp Placement
Clamp Duration
HSOUT Pulse width
Active Interface
PLL Div MSB
PLL Div LSB
VCO/CPMP
Phase Adjust
Clamp Placement
Clamp Duration
HSOUT Pulse width
Active Interface
PLL Div MSB
PLL Div LSB
VCO/CPMP
Phase Adjust
Clamp Placement
Register Name
Register Name
Register Name
R
Register
Address
Register
Address
Register
Address
0x12
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x12
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x12
0x01
0x02
0x03
0x04
0x05
Register
Register
Register
Value
Value
Value
0xD0
0xD4
0xF0
0xB4
0xF0
0x81
0x53
0x80
0x40
0x40
0x88
0x81
0x69
0x70
0x80
0x64
0x64
0x70
0x81
0x86
0x80
0x78
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Force selection of analog input
PLL divider value. XGA60 has 1344 cycles per HSYNC
period. 1344 -1 = 0x53F
VCORNGE = 01, CURRENT = 101
Default phase = T/2
64 cycles after HSYNC
64 cycles in duration
136 cycles in HSYNC
Force selection of analog input
PLL divider value. SXGA60 has 1688 cycles per HSYNC
period. 1688 -1 = 0x697
VCORNGE = 10, CURRENT = 100
Default phase = T/2
100 cycles after HSYNC
100 cycles in duration
112 cycles in HSYNC
Force selection of analog input
PLL divider value. UXGA60 has 2160 cycles per HSYNC
period. 2160 -1 = 0x86F
VCORNGE = 10, CURRENT = 101
Default phase = T/2
120 cycles after HSYNC
Description
Description
Description
Bus Interface
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