HW-XGI-SCLK-G Xilinx Inc, HW-XGI-SCLK-G Datasheet
HW-XGI-SCLK-G
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HW-XGI-SCLK-G Summary of contents
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Xilinx Generic Interface (XGI) SuperClock Module User Guide UG091 (v1.1) March 2, 2007 R P/N 0402581-01 ...
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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, ...
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Table of Contents Preface: About This Guide Additional Resources Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Xilinx Generic Interface (XGI) SuperClock Module R UG091 (v1.1) March 2, 2007 ...
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R About This Guide The Xilinx Generic Interface (XGI) SuperClock Module User Guide provides an overview of functionality, operation, and configuration of the SuperClock module add-on board. Additional Resources To find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature. To ...
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Preface: About This Guide Convention Italic font Square brackets [ ] Braces { } Vertical bar | Vertical ellipsis . . . Horizontal ellipsis . . . Online Document The following conventions are used in this document: Convention Blue text ...
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R Xilinx Generic Interface (XGI) SuperClock Module Package Contents • SuperClock module • User guide and schematic • Two 12-inch SMA-to-SMA cable assemblies Introduction The SuperClock module is a highly flexible clock source designed to meet the common needs of ...
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Introduction Figure 1 and Note: Images are intended for reference purposes only and might not reflect the current version of the board. Power Supply Option Headers Control Switch, SW1 Off = Logic Logic 1 XTAL1 Master Reset, ...
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R Functional Description The SuperClock module generates stable, low phase noise, 100Ω differentially terminated reference clock outputs utilizing a crystal-to-3.3V LVPECL frequency synthesizer (843001AG-22) from Integrated Device Technology (IDT) interface provides a platform capable of supporting two selectable clock rate ...
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Functional Description The LVPECL frequency synthesizer receives a stable fundamental frequency from one of two populated crystal oscillators (XTAL0, XTAL1 using the test clock input at SMA J10. Reference clock input selection is set according to the input ...
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R Table 4: N Divider Selection (Continued) Inputs Figure 3 shows the output frequencies supported by the SuperClock module. 49.00-64.00 /10 54.44-71.11 /9 61.25-80.00 /8 70.00-91.43 /7 81.67-106.67 /6 98.00-128. 100 ...
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Functional Description Table 5: Common Configurations (Continued) Input Reference Clock 19.44 19.53125 26.5625 26.5625 26.5625 31.25 Notes: User Tips 1. REF_CLK * M divider value = VCO frequency 2. VCO Frequency / N Divider = ...
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R Power Supply Options The SuperClock module runs off of 5V DC. It can be powered up either through the J11 board interface connector when connected to a compatible host board or through an external power supply. ...
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References LED Representation Control line register status can be viewed through onboard LEDs, as shown in page 9. Master Reset A master reset option is available using either the onboard momentary switch (SW2 using control line J1, pin ...
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VCC D SW1 SEL0 7 10 SEL1 8 9 78RB08ST ...
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VCC VCC C16 C17 C14 1 C15 0.01UF 0.01UF 0.1UF 0.1UF Differential 100 Ohms VCC VCC CLK_SEL CLK_EN Q0 6 PCLK_P C Differential ...