HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet
HW-XGI-VIDEO-US
Specifications of HW-XGI-VIDEO-US
HW-XGI-VIDEO-US
Related parts for HW-XGI-VIDEO-US
HW-XGI-VIDEO-US Summary of contents
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Video Input/Output Daughter Card User Guide UG235 (v1.2.1) October 31, 2007 R ...
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...
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Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Chapter 4: DVI/VGA Input Interface Interface Description DVI Connectivity on VIODC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LVDS Camera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007 ...
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Schedule of Figures Chapter 1: VIODC Overview Figure 1-1: VIODC Attached to an ML402 Platform . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 8-2: Configuration Jumper Locations on the VIODC Top, Configured for VIODC Mounted to an ML402 Board . . . . . . . . . . . . . . . . . . . . . . . ...
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Schedule of Tables Chapter 1: VIODC Overview Chapter 2: VIODC to ML402 Card Interface Table 2-1: VIOBUS Signal Definitions . . . . . . . . . . . . . . . . . . . . . ...
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Appendix B: VSK I/O Connector Location Pictures Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007 ...
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R About This Guide This guide describes the Video Input and Output Daughter Card (VIODC), a standard video interface card that is compatible with the Xilinx ML401, ML402, and ML403 development platforms. Guide Contents This manual contains the following chapters: ...
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Preface: About This Guide Conventions This document uses the following conventions. An example illustrates each convention. Typographical The following typographical conventions are used in this document: Convention Courier font Courier bold Helvetica bold Italic font Square brackets [ ] Braces ...
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R Online Document The following conventions are used in this document: Convention Blue text Red text Blue, underlined text Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 Meaning or Use See the section Cross-reference link to a Resources” location ...
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Preface: About This Guide 14 www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 R ...
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R VIODC Overview Introduction The Video Input and Output Daughter Card (VIODC standard video interface card for Xilinx development platforms compatible with ML401, ML402, and ML403 boards and other future Xilinx development platforms. The VIODC is ...
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Chapter 1: VIODC Overview ML402 Platform Video Interface Support The VIODC supports the following video interfaces: • LVDS Camera Input Port – The LVDS camera input port supports the Irvine Sensors LVDS RGB camera with a Micron MT9V022 1/3 inch ...
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R • SDI Video Interface – A complete SDI video interface capable of supporting both SD and HD video rates is available on the VSK. The SDI standard is a high-speed serial interface used to carry digital video over coax ...
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Chapter 1: VIODC Overview 18 www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 R ...
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R VIODC to ML402 Card Interface When the VIODC is used as part of the Video Starter Kit (VSK) from Xilinx, the 64-pin XGI connector connects the VIODC to a ML402 card to communicate with the VIODC card. When the ...
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Chapter 2: VIODC to ML402 Card Interface VIOBUS Signal Definitions Table 2-1: VIOBUS Signal Definitions Signal Description VIO Data Bus (a moderate-speed single-ended bus) vio_up[25:0] Data bus to the VIODC vio_up_ena Pixel enable for vio_up[25:0] vio_dn[25:0] Data bus from the ...
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R Component and S-Video Interfaces Overview The VIODC board supports input and output for S-video, composite, and component video. Figure 3-1 S-Video ADA4412 Composite ADV7403 Component ADA4412 Figure 3-1: S-Video, Composite, and Component Video Input and Output Block Diagram Input ...
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Chapter 3: Component and S-Video Interfaces definitions. For complete details, refer to the Analog Devices data sheet found at www.analog.com ADV7321 Video Encoder The Analog Devices ADV7321 video encoder device is a single monolithic chip that performs multiple format digital-to-analog ...
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Figure 3-2: S-Video, Composite, and Component Input and Output Signal Conditioning Circuit Video ...
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Chapter 3: Component and S-Video Interfaces ADV7403 S-Video Input The Y (intensity) and C (color) conditioned signals are input into the A12 and A10 of the ADV7403 twelve input analog multiplexer, which routes each of the selected input signals to ...
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R FPGA for further processing. A digital video data stream with control is converted to a composite video stream by the ADV7321A device and associated signal conditioning circuits. The data stream and control is supplied by the FPGA. Composite Video ...
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Chapter 3: Component and S-Video Interfaces Component Video Input and Output Component Video Input RCA style connector J19 (X1, X3 and X5) enable input of analog component video signals, which are then converted to the digital domain by the Analog ...
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R synchronization signals and field indicator. ADV7403 video decoder device to the XC2VP4 Xilinx FPGA. Figure 3-4: Connections from ADV7403 Video Decoder to XC2VP4 FGPA Component Video Output Compliant digital video streams are feed into the ADV7321 device by the ...
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Chapter 3: Component and S-Video Interfaces Analog Output Signal Conditioning Output analog signals are first conditioned to meet standards requirements and then connected to the red, green and blue RCA type connectors X2, X4 and X6 respectively. Analog output is ...
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R Table 3-1: Configuration Modes for ADV7403 Video Decoder Chip (Continued) Register Name 720P Primary Mode Video Standard Enable XTAL ADC Power and PLL Bias Control TLLC Control ADC sw1 ADC sw2 1080I Primary Mode Video Standard Enable XTAL ADC ...
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Chapter 3: Component and S-Video Interfaces Table 3-1: Configuration Modes for ADV7403 Video Decoder Chip (Continued) Register Name TLLC control ADC sw1 ADC sw2 Notes: 1. The ADC sw1 and sw2 are unique to the VIODC input configuration. Refer to ...
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R Table 3-2: Configuration Modes for ADV7321A Video Encoder Chip (Continued) Register Name Input Mode Mode HD Mode Reg 1 HD Mode Reg 2 HD Mode Reg 4 HD Mode Reg 6 525PS Power Mode Input Mode Mode HD Mode ...
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Chapter 3: Component and S-Video Interfaces Table 3-2: Configuration Modes for ADV7321A Video Encoder Chip (Continued) Register Name HD Mode Reg 6 720P Power Mode Input Mode Mode HD Mode Reg 1 HD Mode Reg 2 HD Mode Reg 4 ...
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R DVI/VGA Input Interface This chapter describes the DVI and VGA input interface theory of operation. It covers the signals and presents an overview of the internal operating modes of the AD9887. Users can refer to the Interface Description The ...
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Chapter 4: DVI/VGA Input Interface DVI Interface The DVI interface is through the DVI-I connector. The video data is carried by four differential pairs, three data and a clock. VGA interface The analog VGA interface is through the either the ...
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R 2 pixel(s)/clock mode and features an intra-pair skew tolerance one full clock cycle. With the inclusion of HDCP, displays can now receive encrypted video content. The AD9887A allows for authentication of a video receiver, decryption of ...
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Chapter 4: DVI/VGA Input Interface The HSYNC and VSYNC signals are critical to the VGA interface, but can be encoded in several ways. The most basic is with separate sync signals for each, increasing the number of signals to 5: ...
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R (black arrows also important to note that the VCO frequency range and charge pump currents must be configured to match the expected frequency. Setting the feedback divider correctly results in the correct sample frequency, but the sample ...
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Chapter 4: DVI/VGA Input Interface The VSOUT output is an unmodified signal from the selected source. In analog mode with separate syncs simply a passthrough from the VSYNC input. If the analog input is using a composite sync ...
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R Table 4-3: Analog XGA60 Register Register Name Address Active Interface 0x12 PLL Div MSB 0x01 PLL Div LSB 0x02 VCO/CPMP 0x03 Phase Adjust 0x04 Clamp Placement 0x05 Clamp Duration 0x06 HSOUT Pulse width 0x07 Table 4-4: Analog SXGA60 Register ...
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Chapter 4: DVI/VGA Input Interface Table 4-5: Analog UXGA60 (Continued) Register Register Name Address Clamp Duration 0x06 HSOUT Pulse width 0x07 DVI DVI does not require different settings for different resolutions. Table 4-6: DVI Register Register Name Address Active Interface ...
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R DVI/VGA Output Interface Overview The VIODC supports both digital and analog outputs over the DVI output connector. The interface supports standards up to UXGA (165 MHz pixel clock). By connecting a VGA to the DVI adapter to the DVI ...
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Chapter 5: DVI/VGA Output Interface TPF410 I2C Configuration The DVI device is initialized with a single write of 0x3f to location 0x08. The DVI I2C interface is mapped to location 0x70/0x71. Table 5-1: Configuration Modes for TPF410 I2C Video Encoder ...
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R SDI Interface Introduction This chapter describes how the demo is implemented. More detailed descriptions of how to implement SD-SDI and HD-SDI transmitters and receivers can be found in Xilinx application notes, XAPP683, XAPP684, XAPP579, and various other SDI-related Xilinx ...
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Chapter 6: SDI Interface Table 6-1 shows the various frequencies produced by the PLL502 and ICS664-02 when configured for the three different SDI bit rates. In SD-SDI mode, the 54 MHz clock out of the ICS664-02 is multiplied by two ...
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R In HD-SDI mode, there are two possible bit rates, 1.485 Gb/s and 1.4835 Gb/s. These require 74.25 MHz and 74.1758 MHz reference clock frequencies, respectively. The ICS664-02 frequency synthesizer can produce both of these frequencies. The RocketIO receiver uses ...
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Chapter 6: SDI Interface The code running on the PicoBlaze processor also provides an interactive debugging capability for viewing and changing the contents of the registers in the ADV7321B encoder. A ChipScope™ Pro VIO module is instantiated in the design ...
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R Table 6-3: ADV7321B HD Mode Register 1 (0x10) Settings by Video Format HD Video Format 1080i25 All others Table 6-4: Register Name Power mode Mode select SD mode 0 SD mode 1 SD mode 3 SD mode 6 SD ...
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Chapter 6: SDI Interface Table 6-5: Register Name SD Fsc 2 SD Fsc 3 SDI Transmitter Figure 6-3 provides either 74.25 MHz or 74.1758 MHz in HD mode or 54 MHz in SD mode. This reference clock is connected directly ...
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R error detection CRC values, forms them into an EDH packet, and inserts the packet into the appropriate place in the video stream. The video stream is encoded for transmission by the SD-SDI scrambler. Finally, every encoded bit from the ...
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Chapter 6: SDI Interface 50 www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 R ...
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R Image Sensor Camera Interface LVDS Camera Interface The LVDS camera interfaces the Irvine Sensors LVDS RGB camera with a Micron MT9V022 1/3 inch CMOS image sensor. The camera provides 752 x 480 pixels progressive scan. It ...
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Chapter 7: Image Sensor Camera Interface MHz. Normally, the camera output serial data includes 8 data bits plus HSYNC and VSYNC, plus a START and STOP bit. Optionally, the output can be configured to include 10-bit data, with HSYNC and ...
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R Attaching the VIODC to the ML40x Development Board The VIODC can be used in a standalone mode or mounted to a ML401, ML402, or ML403 development board. When the VIODC board is mounted on the ML40x, several jumpers are ...
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Chapter 8: Attaching the VIODC to the ML40x Development Board J16 Figure 8-1: Configuration Jumper Locations on the ML40x Bottom, Configured for VIODC Mounted to an ML402 Board ML402 MOTHERBOARD Figure 8-2: Configuration Jumper Locations on the VIODC Top, Configured ...
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R Reference Information Schematic and Data Sheet Links VIODC schematic ML402 schematic Table A-1: VIODC ICs Manufacturer Part Number ANALOG_DEVICES AD9887AKS-170 ANALOG_DEVICES ADV7321AKST ANALOG_DEVICES ADV7403AKSTZ-140 ANALOG_DEVICES ADV7123JST330 GENNUM GS1524-CKD GENNUM GS1528-CKA ICS ICS1523MLFT ICS ICS664G-02LFTR MAXIM MAX5206ACUB Micron M9T22V PHASELINK ...
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Appendix A: Reference Information VIOBUS Pinouts Table A-2: VIOBUS Signals XGI Header Connections VIOBUS Single-Ended Mode Signal Name vio_up0 vio_up1 vio_up2 vio_up3 vio_up4 vio_up5 vio_up6 vio_up7 vio_up8 vio_up9 vio_up10 vio_up11 vio_up12 vio_up13 vio_up14 vio_up15 vio_dn0 vio_dn1 vio_dn2 vio_dn3 vio_dn4 vio_dn5 ...
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R Table A-2: VIOBUS Signals XGI Header Connections (Continued) VIOBUS Single-Ended Mode Signal Name vio_dn13 vio_dn14 vio_dn15 vio_up16 vio_up17 vio_up18 vio_up9 vio_up20 vio_up21 vio_up22 vio_up23 vio_up24 vio_up25 vio_up_clk_ena vio_dn16 vio_dn17 vio_dn18 vio_dn19 vio_dn20 vio_dn21 vio_dn22 vio_dn23 vio_dn24 vio_dn25 vio_dn_clk_ena vio_reset ...
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Appendix A: Reference Information Table A-2: VIOBUS Signals XGI Header Connections (Continued) VIOBUS Single-Ended Mode Signal Name vio_i2c_sda_dn vio_i2c_sda_up vio_up_clk_lvds_N vio_up_clk_lvds_P Table A-3: VIOBUS ML402 FPGA Connections VIOBUS Single- VIOBUS Ended Mode Differential Mode Signal Name Signal Name vio_up0 vio_up_lvds0_N ...
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R Table A-3: VIOBUS ML402 FPGA Connections (Continued) VIOBUS Single- VIOBUS Ended Mode Differential Mode Signal Name Signal Name vio_dn7 vio_dn_lvds3_P vio_dn8 vio_dn_lvds4_N vio_dn9 vio_dn_lvds4_P vio_dn10 vio_dn_lvds5_N vio_dn11 vio_dn_lvds5_P vio_dn12 vio_dn_lvds6_N vio_dn13 vio_dn_lvds6_P vio_dn14 vio_dn_lvds7_N vio_dn15 vio_dn_lvds7_P vio_up16 vio_up0 vio_up17 ...
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Appendix A: Reference Information Table A-3: VIOBUS ML402 FPGA Connections (Continued) VIOBUS Single- VIOBUS Ended Mode Differential Mode Signal Name Signal Name vio_sport_clk vio_sport_clk vio_sport_sync vio_sport_sync vio_sport_dn vio_sport_dn vio_sport_up vio_sport_up vio_i2c_scl_up vio_i2c_scl_up vio_i2c_sda_dn vio_i2c_sda_dn vio_i2c_sda_up vio_i2c_sda_up vio_up_clk_lvds_N vio_up_clk_lvds_N vio_up_clk_lvds_P vio_up_clk_lvds_P ...
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R Table A-4: VIOBUS VIODC FPGA Connections (Continued) VIOBUS Single- VIOBUS Ended Mode Differential Mode Signal Name Signal Name vio_dn1 vio_dn_lvds0_P vio_dn2 vio_dn_lvds1_N vio_dn3 vio_dn_lvds1_P vio_dn4 vio_dn_lvds2_N vio_dn5 vio_dn_lvds2_P vio_dn6 vio_dn_lvds3_N vio_dn7 vio_dn_lvds3_P vio_dn8 vio_dn_lvds4_N vio_dn9 vio_dn_lvds4_P vio_dn10 vio_dn_lvds5_N vio_dn11 ...
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Appendix A: Reference Information Table A-4: VIOBUS VIODC FPGA Connections (Continued) VIOBUS Single- VIOBUS Ended Mode Differential Mode Signal Name Signal Name vio_dn21 vio_dn5 vio_dn22 vio_dn6 vio_dn23 vio_dn7 vio_dn24 vio_dn8 vio_dn25 vio_dn9 vio_dn_clk_ena vio_dn_clk_ena vio_reset vio_reset vio_sport_clk vio_sport_clk vio_sport_sync vio_sport_sync ...
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R VSK I/O Connector Location Pictures VIODC Connectors LVDS Camera Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 Power ML402 Switch VGA Out 5V Power Input Figure B-1: VIODC Rear View www.xilinx.com Appendix B VIODC VGA In VIODC ML402 ...
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Appendix B: VSK I/O Connector Location Pictures VIODC ML402 DVI In RS-232 64 VIODC DVI/VGA Out Figure B-2: VIODC Left Side View www.xilinx.com R ML402 JTAG Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 ...
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R VIODC SDI Out VIODC SDI IN VIODC VIODC Composite VIODC Y Out Composite In Out Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 VIODC VIODC VIODC VIODC Pb Out Pr Out Figure B-3: VIODC ...
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Appendix B: VSK I/O Connector Location Pictures LVDS Camera 66 Figure B-4: LVDS Camera www.xilinx.com R LVDS Camera HOST Port Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 ...
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R ML402 Board Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 Figure B-5: ML402 Board www.xilinx.com ML402 Board 67 ...
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Appendix B: VSK I/O Connector Location Pictures 68 Figure B-6: ML402 Evaluation Platform www.xilinx.com R Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007 ...