HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 36

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 4: DVI/VGA Input Interface
Table 4-1: VGA Standards
Setting the PLL and Phase
36
VGA60
XGA60
SXGA60
UXGA60
Clock
(MHz)
Freq
Pix
108
162
40
65
The HSYNC and VSYNC signals are critical to the VGA interface, but can be encoded in
several ways. The most basic is with separate sync signals for each, increasing the number
of signals to 5: RGBHV. These syncs can be active high or low, and different resolutions
typically have different combinations of sync polarity. A second encoding is composite HV,
with HSYNC and VSYNC combined onto a single signal. This is preformed through a
logical XOR of the two signals. The end result looks like the original HSYNC signal, except
that its polarity is inverted during VSYNC. This mode reduces the number of signals to 4.
A third mode of encoding the sync signals is by combining the composite sync signal with
the green data. This is referred to as “sync-on-green” (SOG). As mentioned previously, the
typical signal levels are 0-700mV. SOG offsets this by 300mV to 300mV-1V. The drop from
300mV to 0 is used to indicate the composite sync.
The AD9887A digitizes the analog video waveforms using three 8-bit analog-to-digital
converters. For this analog-to-digital conversion to operate properly, it must sample each
pixel at the appropriate time
To explain VGA sampling theory, it is useful to use a greatly simplified example.
shows a single line from a frame with the horizontal front porch set to 1, the sync length set
to 1, and the horizontal back porch set to 2. The line has 12 active pixels. In order to receive
the video data, these are the only signals available.
Figure 4-5
sample times, the AD9887A includes a PLL that locks to the incoming HSYNC,
multiplying the HSYNC frequency by a factor set by the feedback divider. The frequency
multiplication factor is set to the total number of clock cycles per HSYNC period. For the
Figure 4-5
free-running, so ADC samples occur during blanking (gray arrows) as well as active video
HSync
(kHz)
Freq
37.9
48.4
64
75
illustrates the ideal ADC sampling positions for this line. To generate these
example, the multiplication value is 1+1+2+12 = 16. The PLL in the AD9887A is
Porch
Front
HSYNC
40
24
48
64
RGB
Horizontal Timings
10
Sync
(in clk cycles)
128
136
112
192
11
www.xilinx.com
1
1
(Figure
Figure 4-4: Pixel Sampling
2
Porch
Back
160
248
304
88
0
1
4-4).
2
3
12 Active Pixels
Active
1024
1280
1600
4
800
5
6
7
8
Porch
Front
9
1
3
1
1
10
Video Input/Output Daughter Card
11
1
UG235 (v1.2.1) October 31, 2007
Vertical Timings
1
Sync
4
6
3
3
2
(in Lines)
0
Porch
Back
46
23
29
38
Figure 4-4
Active
1024
1200
600
768
R