HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 30

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 3: Component and S-Video Interfaces
30
ADV7321A Configuration Modes
Table 3-1: Configuration Modes for ADV7403 Video Decoder Chip (Continued)
Refer to the ADV7403 data sheet for other video configurations.
Table
Encoder device for each of the supported video standards.
The ADV7301 is mapped to I2C address 0x54/0x55.
Table 3-2: Configuration Modes for ADV7321A Video Encoder Chip
Notes:
1. The ADC sw1 and sw2 are unique to the VIODC input configuration.
525P
TLLC
control
ADC sw1
ADC sw2
Power Mode
Register
Register
Name
Name
3-2, details the parameters setting for the internal registers of the ADV7321A Video
Register
Address
Register
Address
0x6b
0x85
0x86
0xb3
0x0e
0x52
0x54
0x0e
0x3c
0xc3
0xc4
0x00
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Register
Register
Value
0xC2
0x5d
Value
0x18
0x0b
0x54
0x86
0x80
0x46
0x00
0x00
0xfe
0xFE
PLL qpump
[3:0]cpop_sel(1=20-bit,2=30-bit)
Turn off SSPD as sync is on Y
ENABLE SDTI line count mode
SDTI
[7:4]=adc1
[3:0]=adc0
[7]=sw_en,
[6]=SOG
[3:0]=adc2
Startup sequence
[6]=DACB_luma
[5]=DACC_chroma
[4]=DACD_Y
[3]=DACE_Pr
[2]=DACF_Pb on
[1]=pll_off(1=off)
[0]=sleep(1=sleep)
[7]=DACA_composite
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
Description
Description
R