HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 21

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Component and S-Video Interfaces
Overview
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
Component
Composite
S-Video
Figure 3-1: S-Video, Composite, and Component Video Input and Output Block Diagram
ADV7403 Video Decoder
R
ADA4412
ADA4412
The VIODC board supports input and output for S-video, composite, and component
video.
Input signals are conditioned by a combination of passive components and the ADA4412
device. The conditioned input signals are converted to digital signals by the ADV7403
video decoder device. Digital video output data stream from the FPGA is converted to
analog signals by the ADV7321 video encoder device. The analog output signals are
conditioned by the ADA4410 device.
The video decoder, ADV7403 from Analog Devices, is responsible for converting analog
video signals into a representative digital video data stream. The video encoder,
ADV7321A also from Analog Devices, is responsible for the generation of S-Video,
composite, and component analog video signals from a digital video data stream. Both
devices offer an I
The ADV7403 is a high quality, single chip, multiple format video decoder and graphics
digitizer. This multiple format decoder automatically supports the conversion of PAL,
NTSC, and SECAM standards in the form of composite or S-video into a digital ITU-R
BT.656 format. The component processor is capable of decoding/digitizing a wide
selection of video formats in any color space. Component video standards supported
include: 525i, 625i, 525p, 625p, 720p, 1080i and many other HD standards, as well as
graphic digitization from VGA to SXGA. Converted input signals are output to the output
pixel port, which is connected directly to the FPGA. Under user control, the output pixel
port is configurable to conform to multiple different standards. Selection of the format is
done through commands written to the device over the I
Figure 3-1
ADV7403
2
is a simplified block diagram of input and output.
C control serial bus for control and ancillary data.
Control
Video
Data
I2C
www.xilinx.com
FPGA
Control
Video
Data
I2C
ADV7321A
2
C bus and affects the pins
ADA4410
Chapter 3
ug235_ch3_01_120805
S-Video
Composite
Component
21