HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 29

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
R
Table 3-1: Configuration Modes for ADV7403 Video Decoder Chip (Continued)
720P
1080I
Primary
Mode
Video
Standard
Enable
XTAL
ADC Power
and PLL
Bias Control
TLLC
Control
ADC sw1
ADC sw2
Primary
Mode
Video
Standard
Enable
XTAL
ADC power
and PLL
Bias Control
Register
Name
Register
Address
0x1D
0x1D
0x05
0x06
0x3a
0x3b
0x6b
0x85
0x86
0xb3
0x0e
0x52
0x54
0x0e
0x05
0x06
0x3a
0x3b
0x3c
0xc3
0xc4
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Register
Value
0xC2
0x5d
0x01
0x0a
0x47
0x20
0x80
0x18
0x0b
0x54
0x86
0x80
0x46
0x00
0x00
0x01
0x47
0x21
0x80
0x0c
0xfe
[2:0] =PRIM_MODE
[3:0]= VID_STD
latch clock
External Bias Enable'
PLL qpump
[3:0]cpop_sel(1=20-bit,2=30-bit)
Turn off SSPD as sync is on Y
ENABLE SDTI line count mode
SDTI
[7:4]=adc1
[3:0]=adc0
[7]=sw_en,
[6]=SOG
[3:0]=adc2
Startup sequence
[2:0] =PRIM_MODE
[3:0]= VID_STD
Latch clock
External Bias Enable'
Component Video Input and Output
Description
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