HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 22

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 3: Component and S-Video Interfaces
Video Signal Input and Output Conditioning
S-Video Input and Output
22
ADV7321 Video Encoder
S-Video Input
S-Video Input Signal Conditioning
definitions. For complete details, refer to the Analog Devices data sheet found at
www.analog.com
The Analog Devices ADV7321 video encoder device is a single monolithic chip that
performs multiple format digital-to-analog video encoder functions. Both standard and
high definition input formats are supported including: SMPTE 293M (525p), BTA T-1004
EDTV2 (525p), CCIR-656, and SMPTE 274M. Multiple output standards for both SD and
HD are also supported including: YPrPb HDTV (EIA 770.3), RGB, RGBHV, YPrPb
progressive scan (EIA-770.1, EIA-770.2) and component YPrPb (SMPTE/EBU N10). 4:2:2
or 4:4:4 data format is supported for HDTV. For all standards, external horizontal, vertical
and blanking signals or EAV/SAV timing codes control the insertion of appropriate
synchronization signals into the digital data stream and, therefore, the analog output
signal.
The ADV7321 provides user configuration options through an I
access to a large number of configuration registers. Under user control, the device pins are
reconfigured to match the operation selected. For instance, SD 8-bit mode configuration
only, the data input port S7-S0 would be used to transfer in a multiplexed fashion the
digital video data stream into the device. The Y and C buses would not be used. Refer to
Analog Devices ADV7321 data sheet for further details.
Each of the video input and output signals must be conditioned to ensure that the physical
interfaces meet impedance and electrical specification for each individual video standard.
Figure 3-3
composite and component input and output signals.
Connector J20 provides input and output of S-Video compatible signals. For the input, the
Y (intensity) and C (color) signals are each conditioned and input into the ADV7403 video
decoder to create a digital video data stream output, which is transferred to the Xilinx
XC2VP4 FPGA for handling. Generation of S-Video output starts with a digital video
stream coming from the FPGA, written into the ADV7321A video encoder to product the
Y/C analog outputs, which are conditioned and output to the J20 S-Video connector.
S-Video input signals are first conditioned using two identical circuits illustrated in
Figure
Devices ADA4412 device. This conditioning circuit insures that the input signal
impedance matches the S-Video (IEC 60933-5) specification and signal levels required by
the ADV7403.
3-2. This circuit contains both passive and active components, including the Analog
illustrates the input and output conditioning circuits used for S-video,
www.xilinx.com
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
2
C bus, which enables
R