ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 982
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
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39.6.3
39.6.4
Figure 39-4. EOCx and DRDY Flag Behavior
982
982
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
EOCx
DRDY
CHx
SAM3S Preliminary
SAM3S Preliminary
Conversion Resolution
Conversion Results
Write the ADC_CR
with START = 1
The ADC supports 10-bit or 12-bit resolutions. The 10-bit selection is performed by setting the
LOWRES bit in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is
the highest and the DATA field in the data registers is fully used. By setting the LOWRES bit, the
ADC switches to the lowest resolution and the conversion results can be read in the lowest sig-
nificant bits of the data registers. The two highest bits of the DATA field in the corresponding
ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
Moreover, when a PDC channel is connected to the ADC, 12-bit or 10-bit resolution sets the
transfer request size to 16 bits.
When a conversion is completed, the resulting 12-bit digital value is stored in the Channel Data
Register (ADC_CDRx) of the current channel and in the ADC Last Converted Data Register
(ADC_LCDR). By setting the TAG option in the ADC_EMR, the ADC_LCDR presents the chan-
nel number associated to the last converted data in the CHNB field.
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of
a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either
EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR
clears the DRDY bit and EOC bit corresponding to the last converted channel.
If the ADC_CDR is not read before further incoming data is converted, the corresponding Over-
run Error (OVREx) flag is set in the Overrun Status Register (ADC_OVER).
Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error)
in ADC_SR.
The OVREx flag is automatically cleared when ADC_OVER is read, and GOVRE flag is auto-
matically cleared when ADC_SR is read.
Read the ADC_CDRx
Write the ADC_CR
with START = 1
Read the ADC_LCDR
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
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