ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 321

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4
20.4.1
20.4.2
20.5
20.5.1
20.5.2
6500C–ATARM–8-Feb-11
Product Dependencies
CRCCU Functional Description
Power Management
Interrupt Source
CRC Calculation Unit description
CRC Calculation Unit Operation
The CRCCU is clocked through the Power Management Controller (PMC), the programmer
must first configure the CRCCU in the PMC to enable the CRCCU clock.
The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU
interrupt requires programming the Interrupt Controller before configuring the CRCCU.
The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured
and activated, this CRC engine performs a checksum computation on a Memory Area. CRC
computation is performed from the LSB to MSB bit. Three different polynomials are available
CCIT802.3, CASTAGNOLI and CCIT16, see the bitfield description,
mial” on page
The CRCCU has a DMA controller that supports programmable CRC memory checks. When
enabled, the DMA channel reads a programmable amount of data and computes CRC on the fly.
The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL which need to be mapped
in the internal SRAM. The addresses of these two registers are pointed at by the
CRCCU_DSCR register.
Figure 20-2. CRCCU Descriptor Memory Mapping
TR_ADDR defines the start address of memory area targeted for CRC calculation.
TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the
transfer-completed interrupt enable.
335, for details.
CRCCU_DSCR+0x10
CRCCU_DSCR+0xC
CRCCU_DSCR+0x8
CRCCU_DSCR+0x0
CRCCU_DSCR+0x4
SAM3S Preliminary
TR_ADDR
TR_CTRL
Reserved
Reserved
TR_CRC
Memory
SRAM
“PTYPE: Primitive Polyno-
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