ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 618
ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
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31.6.2
31.6.3
31.7
31.7.1
Figure 31-3.
Figure 31-4. Transfer Format
31.7.2
618
Functional Description
SAM3S Preliminary
Power Management
Interrupt
Transfer Format
Modes of Operation
START and STOP Conditions
TWD
TWCK
The TWI interface may be clocked through the Power Management Controller (PMC), thus the
programmer must first configure the PMC to enable the TWI clock.
The TWI interface has an interrupt line connected to the Nested Vector Interrupt Controller
(NVIC). In order to handle interrupts, the NVIC must be programmed before configuring the TWI.
Table 31-5.
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see
31-4).
Each transfer begins with a START condition and terminates with a STOP condition (see
31-3).
The TWI has six modes of operations:
• Enable the peripheral clock.
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
• Master transmitter mode
• Master receiver mode
Start
Instance
TWI0
TWI1
Address
TWCK
TWD
Peripheral IDs
R/W
Start
Ack
19
20
ID
Data
Ack
Data
Stop
Ack
Stop
6500C–ATARM–8-Feb-11
Figure
Figure
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