ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 291
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
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18. Enhanced Embedded Flash Controller (EEFC)
18.1
18.2
18.2.1
18.2.2
18.3
18.3.1
6500C–ATARM–8-Feb-11
Description
Product Dependencies
Functional Description
Power Management
Interrupt Sources
Embedded Flash Organization
The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with
the 32-bit internal bus.
Its 128-bit or 64-bit wide memory interface increases performance. It also manages the pro-
gramming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system
about the Flash organization, thus making the software generic.
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Man-
agement Controller has no effect on its behavior.
The Enhanced Embedded Flash Controller (EEFC) interrupt line is connected to the Nested
Vectored Interrupt Controller (NVIC). Using the Enhanced Embedded Flash Controller (EEFC)
interrupt requires the NVIC to be programmed first. The EEFC interrupt is generated only on
FRDY bit rising.
Table 18-1.
The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is
composed of:
The embedded Flash size, the page size, the lock regions organization and GPNVM bits defini-
tion are described in the product definition section. The Enhanced Embedded Flash Controller
(EEFC) returns a descriptor of the Flash controlled after a get descriptor command issued by the
application (see
• One memory plane organized in several pages of the same size.
• Two 128-bit or 64-bit read buffers used for code read optimization.
• One 128-bit or 64-bit read buffer used for data read optimization.
• One write buffer that manages page programming. The write buffer size is equal to the page
• Several lock bits used to protect write/erase operation on several pages (lock region). A lock
• Several bits that may be set and cleared through the Enhanced Embedded Flash Controller
size. This buffer is write-only and accessible all along the 1 MByte address space, so that
each word can be written to its final address.
bit is associated with a lock region composed of several pages in the memory plane.
(EEFC) interface, called General Purpose Non Volatile Memory bits (GPNVM bits).
Instance
EFC
Peripheral IDs
“Getting Embedded Flash Descriptor” on page
ID
6
SAM3S Preliminary
296).
291
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