ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 492
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
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Figure 28-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes
28.5.11
28.5.12
28.5.13
28.5.13.1
28.5.13.2
492
492
Read PIO_ISR
Pin Level
PIO_ISR
SAM3S Preliminary
SAM3S Preliminary
MCK
I/O Lines Lock
Programmable Schmitt Trigger
Parallel Capture Mode
Overview
Functional Description
The other lines are configured in Falling Edge or Low Level detection by default, if they have not
been previously configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low
Level detection by writing 32’h0000_004A in PIO_FELLSR.
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller
PWM), it can become locked by the action of this peripheral via an input of the PIO controller.
When an I/O line is locked, the write of the corresponding bit in the registers PIO_PER,
PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER, PIO_ABCDSR1 and
PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime
which I/O line is locked by reading the PIO Lock Status register PIO_LOCKSR. Once an I/O line
is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller.
It is possible to configure each input for the Schmitt Trigger. By default the Schmitt trigger is
active. Disabling the Schmitt Trigger is requested when using the QTouch
The PIO Controller integrates an interface able to read data from a CMOS digital image sensor,
a high-speed parallel ADC, a DSP synchronous port in synchronous mode, etc.... For better
understanding and to ease reading, the following description uses an example with a CMOS dig-
ital image sensor.
The CMOS digital image sensor provides a sensor clock, an 8-bit data synchronous with the
sensor clock, and two data enables which are synchronous with the sensor clock too.
APB Access
APB Access
™
Library.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
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