ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 700
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
- Current page: 700 of 1118
- Download datasheet (24Mb)
Figure 33-26. Break Transmission
33.7.3.14
33.7.3.15
700
700
Baud Rate
TXEMPTY
US_CR
TXRDY
Clock
Write
TXD
SAM3S Preliminary
SAM3S Preliminary
Receive Break
Hardware Handshaking
Start
Bit
D0
D1
D2
STTBRK = 1
The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK
commands are taken into account only if the TXRDY bit in US_CSR is to 1 and the start of the
break condition clears the TXRDY and TXEMPTY bits as if a character is processed.
Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All
STPBRK commands requested without a previous STTBRK command are ignored. A byte writ-
ten into the Transmit Holding Register while a break is pending, but not started, is ignored.
After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times.
Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the
start of the next character. If the timeguard is programmed with a value higher than 12, the TXD
line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 33-26
commands on the TXD line.
The receiver detects a break condition when all data, parity and stop bits are low. This corre-
sponds to detecting a framing error with data to 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may
be cleared by writing the Control Register (US_CR) with the bit RSTSTA to 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchro-
nous operating mode or one sample at high level in synchronous operating mode. The end of
break detection also asserts the RXBRK bit.
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins
are used to connect with the remote device, as shown in
D3
D4
D5
D6
D7
illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK)
Parity
Bit
Stop
Bit
Break Transmission
STPBRK = 1
Figure
33-27.
End of Break
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
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