C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 52
![KIT DEV C8051F800](/photos/28/94/289400/mcudevkit_sml.jpg)
C8051F800DK
Manufacturer Part Number
C8051F800DK
Description
KIT DEV C8051F800
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F800DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F800
Data Bus Width
16 bit
Interface Type
USB
Operating Supply Voltage
7 V to 15 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F8xx
Lead Free Status / Rohs Status
Supplier Unconfirmed
Other names
336-1797
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C8051F80x-83x
SFR Definition 8.4. ADC0CN: ADC0 Control
SFR Address = 0xE8; Bit-Addressable
52
Name
Reset
2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select.
Bit
Type
7
6
5
4
3
Bit
AD0BUSY ADC0 Busy Bit.
AD0WINT
AD0INT
AD0TM
AD0EN
Name
AD0EN
R/W
7
0
ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a con-
version is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Delayed Track Mode: When ADC0 is enabled, input is tracked when a conversion
is not in progress. A start-of-conversion signal initiates three SAR clocks of additional
tracking, and then begins the conversion.
ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
000: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101–111: Reserved.
AD0TM
R/W
6
0
AD0INT
R/W
5
0
AD0BUSY AD0WINT
R/W
Rev. 1.0
4
0
Read:
0: ADC0 conversion is not
in progress.
1: ADC0 conversion is in
progress.
Function
R/W
3
0
2
0
Write:
0: No Effect.
1: Initiates ADC0 Conver-
sion if AD0CM[2:0] =
000b
AD0CM[2:0]
R/W
1
0
0
0
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