C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 157

• Manufacturer Part Number: C8051F800DK
• Description: KIT DEV C8051F800
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F800DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F800
• Data Bus Width: 16 bit
• Interface Type: USB
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F8xx
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1797

SFR Definition 23.14. P1SKIP: Port 1 Skip
SFR Address = 0xD5
SFR Definition 23.15. P2: Port 2
SFR Address = 0xA0; Bit-Addressable
Name
Reset
Name
Reset
Bit
7:0
Bit
7:1
Type
Type
0
Bit
Bit
Unused
P1SKIP[7:0]
Name
P2[0]
Name
0*
R
7
7
0
Unused.
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
Note: P1.4–P1.7 are not available on 16-pin packages, with the reset value of 1111b for
0*
R
6
6
0
Description
P1SKIP[7:4].
0*
R
5
5
0
Rev. 1.0
Don’t Care
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0*
R
4
4
0
P1SKIP[7:0]
R/W
Function
Write
R
3
0
3
0
C8051F80x-83x
R
2
0
2
0
0000000b
0: P2.0 Port pin is logic
LOW.
1: P2.0 Port pin is logic
HIGH.
R
1
0
1
0
Read
P2[0]
R/W
0
0
0
1
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