C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 125

• Manufacturer Part Number: C8051F800DK
• Description: KIT DEV C8051F800
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F800DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F800
• Data Bus Width: 16 bit
• Interface Type: USB
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F8xx
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1797

21.2. Power-Fail Reset / V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 21.2). When V
to a level above V
contents are not altered by the power-fail reset, it is impossible to determine if V
required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
enabled and selected as a reset source after power-on resets. Its defined state (enabled/disabled) is not
altered by any other reset source. For example, if the V
is performed, the V
Important Note: If the V
is selected as a reset source. Selecting the V
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
state is shown below:
1. Enable the V
2. If necessary, wait for the V
3. Select the V
See Figure 21.2 for V
monitor reset. See Section “7. Electrical Characteristics” on page 39 for complete electrical characteristics
of the V
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monitor.
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RST
monitor as a reset source (PORSF bit in RSTSRC = 1).
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monitor (VDMEN bit in VDM0CN = 1).
, the CIP-51 will be released from the reset state. Even though internal data memory
monitor will still be disabled after the reset.
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monitor timing; note that the power-on-reset delay is not incurred after a V
monitor is being turned on from a disabled state, it should be enabled before it
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monitor to stabilize.
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Monitor
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monitor and configuring it as a reset source from a disabled
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Rev. 1.0
monitor as a reset source before it is enabled and stabi-
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monitor is disabled by code and a software reset
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to drop below V
C8051F80x-83x
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dropped below the level
RST
, the power supply
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monitor is
returns
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