C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 237

• Manufacturer Part Number: C8051F800DK
• Description: KIT DEV C8051F800
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F800DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F800
• Data Bus Width: 16 bit
• Interface Type: USB
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F8xx
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1797

set is then given (in PCA clocks) by Equation 29.5, where PCA0L is the value of the PCA0L register at the
time of the update.
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF2 flag (PCA0CN.2) while the WDT is
enabled.
29.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
1. Disable the WDT by writing a 0 to the WDTE bit.
2. Select the desired PCA clock source (with the CPS2–CPS0 bits).
3. Load PCA0CPL2 with the desired WDT update offset value.
4. Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
5. Enable the WDT by setting the WDTE bit to 1.
6. Reset the WDT timer by writing to PCA0CPH2.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 29.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 29.3 lists some example time-
out intervals for typical system clocks.
29.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
mode).
Notes:
System Clock (Hz)
Equation 29.5. Watchdog Timer Offset in PCA Clocks
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Offset
24,500,000
24,500,000
24,500,000
3,062,500
3,062,500
3,062,500
Table 29.3. Watchdog Timer Timeout Intervals
of 0x00 at the update time.
32,000
32,000
32,000
=
2
2
2

256 PCA0CPL2

PCA0CPL2
Rev. 1.0
255
128
255
128
255
128
32
32
32

+

256 PCA0L
Timeout Interval (ms)
–
24576
12384
129.5
3168
C8051F80x-83x
32.1
16.2
33.1
257
4.1

1
237