C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 36

KIT DEV C8051F800

C8051F800DK

Manufacturer Part Number
C8051F800DK
Description
KIT DEV C8051F800
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F800DK

Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F800
Data Bus Width
16 bit
Interface Type
USB
Operating Supply Voltage
7 V to 15 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F8xx
Lead Free Status / Rohs Status
Supplier Unconfirmed
Other names
336-1797
C8051F80x-83x
36
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
pad is to be 60 µm minimum, all the way around the pad.
solder paste release.
Components.
Dimension
C
E
X
Y
Table 5.2. QSOP-24 PCB Land Pattern Dimensions
 
Figure 5.2. QSOP-24 PCB Land Pattern
Rev. 1.0
5.20
0.30
1.50
Min
0.635 BSC
Max
5.30
0.40
1.60

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