C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 138

• Manufacturer Part Number: C8051F800DK
• Description: KIT DEV C8051F800
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F800DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F800
• Data Bus Width: 16 bit
• Interface Type: USB
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F8xx
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1797

C8051F80x-83x
23. Port Input/Output
Digital and analog resources are available through 17 I/O pins (24-pin and 20-pin packages) or 13 I/O pins
(16-pin packages). Port pins P0.0–P1.7 can be defined as general-purpose I/O (GPIO) or assigned to one
of the internal digital resources as shown in Figure 23.4. Port pin P2.0 can be used as GPIO and is shared
with the C2 Interface Data signal (C2D). The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in
the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 23.5). The registers XBR0 and XBR1, defined in SFR Definition 23.1 and SFR Definition 23.2, are
used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 23.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Section “7. Electrical Characteristics” on page 39.
138
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
CP0
PCA
SPI
(P0.0-P0.7)
(P1.0-P1.7)
Figure 23.1. Port I/O Functional Block Diagram
2
4
2
2
4
2
8
8
(ADC0, CP0, VREF, XTAL)
To Analog Peripherals
PnSKIP Registers
Rev. 1.0
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
To CS0
8
8
*Note: P1.4-P1.7
are not available
on the 16-pin
packages.
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Cells
Cells
Cells
I/O
I/O
P1
I/O
P2
P0
External Interrupts
PnMDIN Registers
EX0 and EX1
PnMDOUT,
P0.0
P0.7
P1.0
P1.7*
P2.0